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| Preliminary User's Manual www..com PD780973 Subseries 8-Bit Single-Chip Microcontrollers PD780973(A) PD78F0974 Document No. U12406EJ2V0UM00 (2nd edition) Date Published May 1998 N CP(K) (c) Printed in Japan 1997 [MEMO] www..com 2 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need www..com to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. EEPROM, FIP, and IEBus are trademarks of NEC Corporation. Windows and WindowsNT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. Ethernet is a trademark of Xerox Corporation. NEWS and NEWS-OS are trademarks of Sony Corporation. OSF/Motif is a trademark of OpenSoftware Foundation, Inc. TRON is an abbreviation of The Realtime Operating system Nucleus. ITRON is an abbreviation of Industrial TRON. 3 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. License not needed : PD78F0974GF-3B9 The customer must judge the need for license : PD780973GF(A)-xxx-3B9 The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. www..com This product is produced and sold based on the licensed agreement with CP8 Transac concerning EEPROMcontained microcontroller. This product cannot be used for an IC card (SMART CARD). The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M7 96.5 4 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information www..com * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Cumbica-Guarulhos-SP, Brasil Tel: 011-6465-6810 Fax: 011-6465-6829 J98. 2 5 MAJOR REVISIONS IN THIS EDITION (1/2) Page p.38 Description Table 2-1. Pin Input/Output Circuit Types Correction of ports 8 and 9 input/output circuit types Figure 2-1. I/O Circuits of Pins Change of type 17-A to type 17-G Addition of oscillator mode register to Table 3-5. Special Function Register List 4.1 EEPROM Functions Change of the number of rewrite frequency per 1 byte as follows: 10,000 times 100,000 times p.77 www..com 5.2.3 Port 2 * Correction of description * Correction of Figure 5-4. P20 to P27 Block Diagram 5.2.4 Port 3 * Correction of description * Correction of Figure 5-5. P30 to P37 Block Diagram 5.2.8 Port 8 * Correction of description * Addition of Figure 5-9. P81 Block Diagram * Correction of Figure 5-10. P82 to P87 Block Diagram 5.2.9 Port 9 * Correction of description * Correction of Figure 5-11. P90 to P97 Block Diagram Table 5-3. Port Mode Register and Output Latch Settings when Using Alternate Functions * Change of Pxx setting values of P20 to P27 and P30 to P37 from 0 to x * Change of Note 2 p.86 p.89 Addition of Note in Figure 5-13. Port Mode Register (PM2, PM3) Format CHAPTER 6 CLOCK GENERATOR * Addition of oscillator mode register to Table 6-1. Clock Generator Configuration * Change of Figure 6-1. Clock Generator Block Diagram * Addition of (2) Oscillator mode register (OSCM) to 6.3 Clock Generator Control Register * Addition of explanation of oscillator mode register to 6.5 Operation of Clock Generator 13.6 Cautions on Emulation Change of in-circuit emulator of (1) D/A converter mode register (DAM1) as follows: IE-78001-R-A IE78K0-NS Addition of (2) A/D converter of IE-780974-NS-EM1 16.9 Cautions on Emulation Change of in-circuit emulator of (1) LCD timer control register (LCDTM) as follows: IE-78001-R-A IE78K0-NS 17.1 Sound Generator Function Correction of description on (1) Basic cycle output signal (with/without amplitude) 18.2 Meter Controller/Driver Configuration Addition of Cautions to (1) Free running up counter (MCNT) Table 20-1. HALT Mode Operating Status Correction of HALT mode operating status of A/D converter Operable Operation stops p.40 p.54 p.67 p.78 p.82 p.83 p.85 p.163 p.203 p.205 p.214 p.247 The mark shows major revised points. 6 MAJOR REVISIONS IN THIS EDITION (2/2) Page p.255 p.257 p.279 Description Addition of oscillator mode register to Table 21-1. Hardware Status after Reset Change of Note in Table 22-1. Differences between PD78F0974 and PD780973(A) APPENDIX A DEVELOPMENT TOOLS * Support of in-circuit emulator IE-78K0-NS * Change in supported OS * Addition of A.4 Upgrading Former In-circuit Emulator for 78K/0 Series to IE-78001-R-A * Deletion of OS for IBM PC from previous edition * Deletion of Development Environment when Using IE-78000-R-A from previous edition APPENDIX B EMBEDDED SOFTWARE * Change in supported OS * Deletion of Fuzzy Inference Development Support System from previous edition p.291 www..com The mark shows major revised points. 7 INTRODUCTION Readers This manual has been prepared for user engineers who want to understand the functions of the PD780973 Subseries and design and develop its application systems and programs. Purpose This manual is designed to help users understand the following functions using the organization below. Organization www..com The PD780973 Subseries manual is separated into two parts: this manual and the instruction edition (common to the 78K/0 Series). PD780973 Subseries User's Manual (This Manual) * Pin functions * Internal block functions * Interrupt * Other on-chip peripheral functions 78K/0 Series User's Manual Instructions * CPU functions * Instruction set * Explanation of each instruction How to Read This Manual This manual assumes general knowledge of electric engineering, logic circuits, and microcontrollers. * To understand the functions of the PD780973(A) and 78F0974 in general: Read this manual in the order of the CONTENTS. * How to read register formats: The name of a bit whose number is enclosed in square is reserved for the RA78K/ 0 and is defined for the CC78K/0 by the header file sfrbit.h. * To learn the detailed functions of a register whose register name is known: Refer to APPENDIX C REGISTER INDEX. The application examples in this manual are for the "standard" model for generalpurpose electronic systems. If the examples in this manual are to be used for applications where a quality higher than that of the "special" model is required, study the quality grade of the respective components and circuits actually used. Conventions Data significance Active low representation Note Caution Remark Numerical representation : Higher digits on the left and lower digits on the right : xxx (overscore over pin or signal name) : Footnote for item marked with Note in the text : Information requiring particular attention : Supplementary information : Binary Decimal *** xxxx or xxxxB *** xxxx Hexadecimal *** xxxxH 8 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. * Related documents for PD780973 Subseries Document No. Document Name Japanese U12759J U12646J U12406J U12326J U10903J U10904J U12748J English U12759E U12646E This manual U12326E -- -- -- PD780973(A) Preliminary Product Information PD78F0974 Preliminary Product Information PD780973 Subseries User's Manual 78K/0 Series User's Manual Instructions 78K/0 Series Instruction Table www..com 78K/0 Series Instruction Set PD780973 Subseries Special Function Register Table * Related documents for development tool (User's Manual) Document No. Document Name RA78K0 Assembler Package Operation Assembly Language Structured Assembly Language RA78K Series Structured Assembler Preprocessor CC78K0 C Compiler Operation Language CC78K/0 C Compiler Application Note CC78K Series Library Source File IE-78K0-NS IE-78001-R-A SM78K0 System Simulator WindowsTM Base SM78K Series System Simulator Reference External Part User Open Interface Specifications Reference Reference Reference Guide Programming Know-how Japanese U11802J U11801J U11789J EEU-817 U11517J U11518J U13034J U12322J To be prepared To be prepared U10181J U10092J English U11802E U11801E U11789E EEU-1402 U11517E U11518E EEA-1208 -- To be prepared To be prepared U10181E U10092E ID78K0-NS Integrated Debugger PC Base ID78K0 Integrated Debugger EWS Base ID78K0 Integrated Debugger PC Base ID78K0 Integrated Debugger Windows Base U12900J U11151J U11539J U11649J To be prepared -- U11539E U11649E Caution The above documents are subject to change without prior notice. Be sure to use the latest version of a document when starting design. 9 * Related documents for embedded software (User's Manual) Document No. Document Name 78K/0 Series Real-Time OS Basics Installation 78K/0 Series OS MX78K0 Basics Japanese U11537J U11536J U12257J English U11537E U11536E U12257E * Other related documents Document No. Document Name IC Package Manual www..com Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electro Static Discharge (ESD) Guide to Quality Assurance for Semiconductor Devices Microcomputer Product Series Guide Japanese C10943X C10535J C11531J C10983J C11892J -- U11416J C10535E C11531E C10983E C11892E MEI-1202 -- English Caution The above documents are subject to change without prior notice. Be sure to use the latest version of a document when starting design. 10 CONTENTS CHAPTER 1 OUTLINE .................................................................................................................... 1.1 Features ................................................................................................................................ 1.2 Applications ......................................................................................................................... 1.3 Ordering Information ........................................................................................................... 1.4 Quality Grade ....................................................................................................................... 1.5 Pin Configuration (Top View) ............................................................................................. 1.6 78K/0 Series Product Development ................................................................................... 1.7 Block Diagram ...................................................................................................................... 1.8 Outline of Function .............................................................................................................. www..com 23 23 23 24 24 25 27 29 30 31 31 33 33 33 33 34 34 34 35 35 36 36 36 36 36 36 36 36 36 36 36 37 37 CHAPTER 2 PIN FUNCTION .......................................................................................................... 2.1 Pin Function List .................................................................................................................. 2.2 Description of Pin Functions .............................................................................................. 2.2.1 P00 to P07 (Port 0) ..................................................................................................................... 2.2.2 P10 to P14 (Port 1) ..................................................................................................................... 2.2.3 P20 to P27 (Port 2) ..................................................................................................................... 2.2.4 P30 to P37 (Port 3) ..................................................................................................................... 2.2.5 P40 to P44 (Port 4) ..................................................................................................................... 2.2.6 P50 to P54 (Port 5) ..................................................................................................................... 2.2.7 P60, P61 (Port 6) ........................................................................................................................ 2.2.8 P81 to P87 (Port 8) ..................................................................................................................... 2.2.9 P90 to P97 (Port 9) ..................................................................................................................... 2.2.10 COM0 to COM3 .......................................................................................................................... 2.2.11 VLCD ............................................................................................................................................. 2.2.12 AVREF .......................................................................................................................................... 2.2.13 AVSS ............................................................................................................................................ 2.2.14 RESET ........................................................................................................................................ 2.2.15 X1 and X2 ................................................................................................................................... 2.2.16 SMVDD ......................................................................................................................................... 2.2.17 SMVSS ......................................................................................................................................... 2.2.18 VDD .............................................................................................................................................. 2.2.19 VSS .............................................................................................................................................. 2.2.20 VPP (PD78F0974) ...................................................................................................................... 2.2.21 IC (PD780973(A)) ..................................................................................................................... 2.3 Input/output Circuits and Recommended Connection of Unused Pins ......................... 38 41 41 43 44 44 45 CHAPTER 3 CPU ARCHITECTURE .............................................................................................. 3.1 Memory Spaces ................................................................................................................... 3.1.1 Internal program memory space ................................................................................................. 3.1.2 Internal data memory space ....................................................................................................... 3.1.3 Special function register (SFR) area ........................................................................................... 3.1.4 Data memory addressing ............................................................................................................ 3.2 Processor Registers ............................................................................................................ 3.2.1 Control registers ......................................................................................................................... 3.2.2 General registers ........................................................................................................................ 47 47 50 11 3.2.3 Special function registers (SFRs) ............................................................................................... 51 3.3 Instruction Address Addressing ........................................................................................ 3.3.1 Relative addressing .................................................................................................................... 3.3.2 Immediate addressing ................................................................................................................ 3.3.3 Table indirect addressing ............................................................................................................ 3.3.4 Register addressing .................................................................................................................... 55 55 56 57 57 3.4 Operand Address Addressing ............................................................................................ 3.4.1 Implied addressing ...................................................................................................................... 3.4.2 Register addressing .................................................................................................................... 3.4.3 Direct addressing ........................................................................................................................ 3.4.4 Short direct addressing ............................................................................................................... 3.4.5 Special-function register (SFR) addressing ................................................................................ 58 58 59 60 61 62 63 64 64 65 www..com 3.4.6 Register indirect addressing ....................................................................................................... 3.4.7 Based addressing ....................................................................................................................... 3.4.8 Based indexed addressing ......................................................................................................... 3.4.9 Stack addressing ........................................................................................................................ CHAPTER 4 EEPROM ..................................................................................................................... 4.1 EEPROM Functions ............................................................................................................. 4.2 EEPROM Configuration ....................................................................................................... 4.3 EEPROM Control Register .................................................................................................. 4.4 EEPROM Reading ................................................................................................................ 4.5 EEPROM Writing .................................................................................................................. 4.6 EEPROM Control-Related Interrupt ................................................................................... 4.7 Cautions regarding EEPROM Writing ................................................................................ CHAPTER 5 PORT FUNCTIONS ................................................................................................... 5.1 Port Functions ..................................................................................................................... 5.2 Port Configuration ............................................................................................................... 5.2.1 Port 0 .......................................................................................................................................... 5.2.2 Port 1 .......................................................................................................................................... 5.2.3 Port 2 .......................................................................................................................................... 5.2.4 Port 3 .......................................................................................................................................... 5.2.5 Port 4 .......................................................................................................................................... 5.2.6 Port 5 .......................................................................................................................................... 5.2.7 Port 6 .......................................................................................................................................... 5.2.8 Port 8 .......................................................................................................................................... 5.2.9 Port 9 .......................................................................................................................................... 67 67 68 69 70 71 71 72 73 73 75 75 76 77 78 79 80 81 82 83 5.3 5.4 Port Function Control Registers ........................................................................................ Port Function Operations ................................................................................................... 5.4.1 Writing to input/output port .......................................................................................................... 5.4.2 Reading from input/output port ................................................................................................... 5.4.3 Operations on input/output port .................................................................................................. 84 88 88 88 88 CHAPTER 6 CLOCK GENERATOR .............................................................................................. 6.1 Clock Generator Functions ................................................................................................. 6.2 Clock Generator Configuration .......................................................................................... 6.3 Clock Generator Control Register ...................................................................................... 89 89 89 90 12 6.4 System Clock Oscillator ...................................................................................................... 6.4.1 Main system clock oscillator ....................................................................................................... 6.4.2 Divider circuit .............................................................................................................................. 92 92 94 6.5 6.6 Operation of Clock Generator ............................................................................................ Changing Setting of CPU Clock ......................................................................................... 6.6.1 Time required for switching CPU clock ....................................................................................... 6.6.2 Switching CPU clock ................................................................................................................... 95 96 96 97 CHAPTER 7 16-BIT TIMER 0 TM0 ............................................................................................... 7.1 Outline of Internal Timer of PD780973 Subseries ........................................................... 7.2 16-Bit Timer 0 Functions ..................................................................................................... 7.3 16-Bit Timer 0 Configuration .............................................................................................. www..com 7.4 16-Bit Timer 0 Control Registers ........................................................................................ 7.5 16-Bit Timer 0 Operations ................................................................................................... 7.5.1 Pulse width measurement operations ......................................................................................... 99 99 100 102 103 106 106 7.6 16-Bit Timer 0 Cautions ....................................................................................................... 109 111 111 112 113 115 115 CHAPTER 8 8-BIT TIMER 1 TM1 ................................................................................................. 8.1 8-Bit Timer 1 Functions ....................................................................................................... 8.2 8-Bit Timer 1 Configuration ................................................................................................ 8.3 8-Bit Timer 1 Control Registers .......................................................................................... 8.4 8-Bit Timer 1 Operations ..................................................................................................... 8.4.1 8-bit interval timer operation ....................................................................................................... 8.5 8-Bit Timer 1 Cautions ......................................................................................................... 118 119 119 121 122 125 125 127 128 129 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 .............................................. 9.1 8-Bit Timer/Event Counters 2 and 3 Functions ................................................................. 9.2 8-Bit Timer/Event Counters 2 and 3 Configurations ........................................................ 9.3 8-Bit Timer/Event Counters 2 and 3 Control Registers .................................................... 9.4 8-Bit Timer/Event Counters 2 and 3 Operations ............................................................... 9.4.1 8-bit interval timer operation ....................................................................................................... 9.4.2 External event counter operation ................................................................................................ 9.4.3 Square-wave output operation (8-bit resolution) ......................................................................... 9.4.4 8-bit PWM output operation ........................................................................................................ 9.5 8-Bit Timer/Event Counters 2 and 3 Cautions ................................................................... 132 133 133 134 135 136 136 136 CHAPTER 10 WATCH TIMER .......................................................................................................... 10.1 Watch Timer Functions ....................................................................................................... 10.2 Watch Timer Configuration ................................................................................................. 10.3 Watch Timer Control Register ............................................................................................ 10.4 Watch Timer Operations ..................................................................................................... 10.4.1 Watch timer operation ................................................................................................................. 10.4.2 Interval timer operation ............................................................................................................... CHAPTER 11 WATCHDOG TIMER ................................................................................................. 11.1 Watchdog Timer Functions ................................................................................................ 11.2 Watchdog Timer Configuration .......................................................................................... 11.3 Watchdog Timer Control Registers ................................................................................... 139 139 141 141 13 11.4 Watchdog Timer Operations ............................................................................................... 143 11.4.1 Watchdog timer operation ........................................................................................................... 11.4.2 Interval timer operation ............................................................................................................... 143 144 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT .................................................................. 12.1 Clock Output Control Circuit Functions ............................................................................ 12.2 Clock Output Control Circuit Configuration ..................................................................... 12.3 Clock Output Control Circuit Control Registers ............................................................... 12.4 Clock Output Control Circuit Operation ............................................................................ 12.4.1 Clock output operation ................................................................................................................ 145 145 145 146 148 148 www..com 13.1 CHAPTER 13 A/D CONVERTER ..................................................................................................... A/D Converter Functions .................................................................................................... 13.2 A/D Converter Configuration .............................................................................................. 13.3 A/D Converter Control Registers ....................................................................................... 13.4 A/D Converter Operations ................................................................................................... 13.4.1 Basic operations of A/D converter .............................................................................................. 13.4.2 Input voltage and conversion results .......................................................................................... 13.4.3 A/D converter operation mode .................................................................................................... 149 149 150 152 155 155 157 158 13.5 A/D Converter Cautions ...................................................................................................... 160 13.6 Cautions on Emulation ........................................................................................................ 163 CHAPTER 14 SERIAL INTERFACE UART .................................................................................... 14.1 UART Functions ................................................................................................................... 14.2 UART Configuration ............................................................................................................ 14.3 UART Control Registers ...................................................................................................... 14.4 UART Operations ................................................................................................................. 14.4.1 Operation stop mode .................................................................................................................. 14.4.2 Asynchronous serial interface (UART) mode ............................................................................. 165 165 166 167 171 171 171 CHAPTER 15 SERIAL INTERFACE SIO3 ...................................................................................... 15.1 SIO3 Functions .................................................................................................................... 15.2 SIO3 Configuration .............................................................................................................. 15.3 SIO3 Control Register ......................................................................................................... 15.4 SIO3 Operations ................................................................................................................... 15.4.1 Operation stop mode .................................................................................................................. 15.4.2 Three-wire serial I/O mode ......................................................................................................... 183 183 184 185 186 186 187 CHAPTER 16 LCD CONTROLLER/DRIVER ................................................................................... 16.1 LCD Controller/Driver Functions ........................................................................................ 16.2 LCD Controller/Driver Configuration ................................................................................. 16.3 LCD Controller/Driver Control Registers ........................................................................... 16.4 LCD Controller/Driver Settings ........................................................................................... 16.5 LCD Display Data Memory .................................................................................................. 16.6 Common Signals and Segment Signals ............................................................................ 16.7 Supplying LCD Drive Voltage VLC0, VLC1, and VLC2 ........................................................... 16.8 Display Mode ........................................................................................................................ 16.8.1 4-time-division display example .................................................................................................. 189 189 190 192 194 195 196 198 200 200 14 16.9 Cautions on Emulation ........................................................................................................ 203 CHAPTER 17 SOUND GENERATOR .............................................................................................. 17.1 Sound Generator Function ................................................................................................. 17.2 Sound Generator Configuration ......................................................................................... 17.3 Sound Generator Control Registers .................................................................................. 17.4 Sound Generator Operations ............................................................................................. 17.4.1 To output basic cycle signal SGOF (without amplitude) ............................................................. 17.4.2 To output basic cycle signal SGO (with amplitude) ..................................................................... 205 205 206 207 212 212 212 CHAPTER 18 METER CONTROLLER/DRIVER .............................................................................. 18.1 Meter Controller/Driver Functions ..................................................................................... www..com 18.2 Meter Controller/Driver Configuration ............................................................................... 18.3 Meter Controller/Driver Control Registers ........................................................................ 18.4 Meter Controller/Driver Operations .................................................................................... 18.4.1 Basic operation of free-running up counter (MCNT) ................................................................... 18.4.2 To update PWM data .................................................................................................................. 18.4.3 Operation of 1-bit addition circuit ................................................................................................ 18.4.4 PWM output operation (output with 1 clock shifted) ................................................................... 213 213 214 216 220 220 220 221 222 CHAPTER 19 INTERRUPT FUNCTIONS ......................................................................................... 19.1 Interrupt Function Types .................................................................................................... 19.2 Interrupt Sources and Configuration ................................................................................. 19.3 Interrupt Function Control Registers ................................................................................. 19.4 Interrupt Servicing Operations ........................................................................................... 19.4.1 Non-maskable interrupt request acknowledge operation ........................................................... 19.4.2 Maskable interrupt request acknowledge operation ................................................................... 19.4.3 Software interrupt request acknowledge operation .................................................................... 19.4.4 Multiple interrupt servicing .......................................................................................................... 19.4.5 Interrupt request hold .................................................................................................................. 223 223 223 227 234 234 237 239 240 243 CHAPTER 20 STANDBY FUNCTION .............................................................................................. 245 20.1 Standby Function and Configuration ................................................................................ 245 20.1.1 Standby function ......................................................................................................................... 20.1.2 Standby function control register ................................................................................................ 20.2.1 HALT mode ................................................................................................................................. 20.2.2 STOP mode ................................................................................................................................ 245 246 247 250 20.2 Standby Function Operations ............................................................................................ 247 CHAPTER 21 RESET FUNCTION .................................................................................................... 253 21.1 Reset Function ..................................................................................................................... 253 CHAPTER 22 PD78F0974 ............................................................................................................... 257 22.1 Memory Size Switching Register ....................................................................................... 258 22.2 Flash Memory Programming .............................................................................................. 259 22.2.1 Selection of transmission method ............................................................................................... 22.2.2 Flash memory programming function ......................................................................................... 22.2.3 Flashpro II connection ................................................................................................................ 259 260 260 15 CHAPTER 23 INSTRUCTION SET ................................................................................................... 263 23.1 Legend for Operation List ................................................................................................... 264 23.1.1 Operand identifiers and description formats ............................................................................... 23.1.2 Description of "operation" column ............................................................................................... 23.1.3 Description of "flag operation" column ........................................................................................ 264 265 265 23.2 Operation List ...................................................................................................................... 266 23.3 Instructions Listed by Addressing Type ........................................................................... 274 APPENDIX A DEVELOPMENT TOOLS .......................................................................................... A.1 Language Processing Software ......................................................................................... A.2 Flash Memory Writing Tools ............................................................................................... A.3 Debugging Tools ................................................................................................................. www..com 279 282 283 284 284 286 A.3.1 Hardware .................................................................................................................................... A.3.2 Software ...................................................................................................................................... A.4 Upgrading Former In-circuit Emulator for 78K/0 Series to IE-78001-R-A ....................... 288 APPENDIX B EMBEDDED SOFTWARE ......................................................................................... 291 APPENDIX C REGISTER INDEX ..................................................................................................... 293 C.1 Register Index (In Alphabetical Order with Respect to Register Name) ........................ 293 C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ..................... 296 APPENDIX D REVISION HISTORY .................................................................................................. 299 16 LIST OF FIGURES (1/4) Figure No. 2-1. 3-1. 3-2. 3-3. 3-4. 3-5. 3-6. www..com Title I/O Circuits of Pins ............................................................................................................................ Memory Map (PD780973(A)) .......................................................................................................... Memory Map (PD78F0974) ............................................................................................................ Data Memory Addressing (PD780973(A)) ...................................................................................... Data Memory Addressing (PD78F0974) ......................................................................................... Program Counter Configuration ........................................................................................................ Program Status Word Configuration ................................................................................................. Stack Pointer Configuration .............................................................................................................. Data to be Saved to Stack Memory .................................................................................................. Data to be Reset from Stack Memory ............................................................................................... General Register Configuration ........................................................................................................ EEPROM Block Diagram .................................................................................................................. EEPROM Write Control Register (EEWC) Format ........................................................................... Port Types ......................................................................................................................................... P00 to P07 Block Diagram ................................................................................................................ P10 to P14 Block Diagram ................................................................................................................ P20 to P27 Block Diagram ................................................................................................................ P30 to P37 Block Diagram ................................................................................................................ P40 to P44 Block Diagram ................................................................................................................ P50 to P54 Block Diagram ................................................................................................................ P60 and P61 Block Diagram ............................................................................................................. P81 Block Diagram ........................................................................................................................... P82 to P87 Block Diagram ................................................................................................................ P90 to P97 Block Diagram ................................................................................................................ Port Mode Register (PM0, PM4 to PM6, PM8, PM9) Format ........................................................... Port Mode Register (PM2, PM3) Format .......................................................................................... Pull-Up Resistor Option Register (PU0) Format ............................................................................... Clock Generator Block Diagram ....................................................................................................... Processor Clock Control Register (PCC) Format ............................................................................. Oscillator Mode Register (OSCM) Format ........................................................................................ External Circuit of Main System Clock Oscillator .............................................................................. Incorrect Examples of Resonator Connection .................................................................................. Switching CPU Clock ........................................................................................................................ Timer 0 (TM0) Block Diagram ........................................................................................................... 16-Bit Timer Mode Control Register (TMC0) Format ........................................................................ Capture Pulse Control Register (CRC0) Format .............................................................................. Prescaler Mode Register (PRM0) Format ........................................................................................ Configuration Diagram for Pulse Width Measurement by Free-Running Counter ............................ Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) ................................................................... Page 39 41 42 45 46 47 47 49 49 49 50 68 69 73 76 76 77 78 79 80 81 82 82 83 86 86 87 89 90 91 92 93 97 101 103 104 105 106 106 3-7. 3-8. 3-9. 3-10. 4-1. 4-2. 5-1. 5-2. 5-3. 5-4. 5-5. 5-6. 5-7. 5-8. 5-9. 5-10. 5-11. 5-12. 5-13. 5-14. 6-1. 6-2. 6-3. 6-4. 6-5. 6-6. 7-1. 7-2. 7-3. 7-4. 7-5. 7-6. 17 LIST OF FIGURES (2/4) Figure No. 7-7. 7-8. 7-9. 7-10. 8-1. 8-2. www..com 8-3. Title CR0m Capture Operation with Rising Edge Specified ..................................................................... Timing of Pulse Width Measurement Operation by Free-Running Counter (with Both Edges Specified) .............................................................................................................. 16-Bit Timer Register Start Timing .................................................................................................... Capture Register Data Retention Timing .......................................................................................... Timer 1 (TM1) Block Diagram ........................................................................................................... Timer Clock Select Register 1 (TCL1) Format .................................................................................. 8-Bit Timer Mode Control Register 1 (TMC1) Format ....................................................................... Interval Timer Operation Timings ...................................................................................................... Timer 1 Start Timing .......................................................................................................................... Timing after Compare Register Change during Timer Count Operation ........................................... Timer 2 (TM2) Block Diagram ........................................................................................................... Timer 3 (TM3) Block Diagram ........................................................................................................... Timer Clock Select Register 2 (TCL2) Format .................................................................................. Timer Clock Select Register 3 (TCL3) Format .................................................................................. 8-Bit Timer Mode Control Register n (TMCn) Format ....................................................................... Interval Timer Operation Timings ...................................................................................................... External Event Counter Operation Timings (with Rising Edge Specified) ........................................ PWM Output Operation Timing ......................................................................................................... Timing of Operation by Change of CRn ............................................................................................ Timer n Start Timing .......................................................................................................................... Timing after Compare Register Change during Timer Count Operation ........................................... Watch Timer Block Diagram ............................................................................................................. Watch Timer Mode Control Register (WTM) Format ........................................................................ Operation Timing of Watch Timer/Interval Timer ............................................................................... Watchdog Timer Block Diagram ....................................................................................................... Watchdog Timer Clock Select Register (WDCS) Format .................................................................. Watchdog Timer Mode Register (WDTM) Format ............................................................................ Clock Output Control Circuit Block Diagram ..................................................................................... Clock Output Selection Register (CKS) Format ................................................................................ Port Mode Register 6 (PM6) Format ................................................................................................. Remote Control Output Application Example ................................................................................... A/D Converter Block Diagram ........................................................................................................... Power-Fail Detection Function Block Diagram ................................................................................. A/D Converter Mode Register (ADM1) Format ................................................................................. Analog Input Channel Specification Register (ADS1) Format .......................................................... Power-Fail Compare Mode Register (PFM) Format ......................................................................... Basic Operation of 8-Bit A/D Converter ............................................................................................ Relation between Analog Input Voltage and A/D Conversion Result ................................................ Page 107 108 109 109 111 113 114 115 118 118 119 120 122 123 124 125 128 130 131 132 132 133 135 137 139 141 142 145 146 147 148 149 150 152 153 154 156 157 8-4. 8-5. 8-6. 9-1. 9-2. 9-3. 9-4. 9-5. 9-6. 9-7. 9-8. 9-9. 9-10. 9-11. 10-1. 10-2. 10-3. 11-1. 11-2. 11-3. 12-1. 12-2. 12-3. 12-4. 13-1. 13-2. 13-3. 13-4. 13-5. 13-6. 13-7. 18 LIST OF FIGURES (3/4) Figure No. 13-8. 13-9. 13-10. 13-11. 13-12. 14-1. 14-2. www..com Title A/D Conversion ................................................................................................................................. Example of Method of Reducing Current Consumption in Standby Mode ....................................... Analog Input Pin Connection ............................................................................................................ A/D Conversion End Interrupt Request Generation Timing .............................................................. D/A Converter Mode Register (DAM1) Format ................................................................................. UART Block Diagram ........................................................................................................................ Asynchronous Serial Interface Mode Register (ASIM) Format ......................................................... Asynchronous Serial Interface Status Register (ASIS) Format ........................................................ Baud Rate Generator Control Register (BRGC) Format .................................................................. Error Tolerance (when k = 0) including Sampling Errors .................................................................. Format of Transmit/Receive Data in Asynchronous Serial Interface ................................................ Timing of Asynchronous Serial Interface Transmit Completion Interrupt .......................................... Timing of Asynchronous Serial Interface Receive Completion Interrupt ........................................... Receive Error Timing ........................................................................................................................ SIO3 Block Diagram ......................................................................................................................... Serial Operation Mode Register (CSIM) Format ............................................................................... Serial Operation Mode Register (CSIM) Format ............................................................................... Serial Operation Mode Register (CSIM) Format ............................................................................... Three-Wire Serial I/O Mode Timing .................................................................................................. LCD Controller/Driver Block Diagram ............................................................................................... LCD Clock Select Circuit Block Diagram .......................................................................................... LCD Display Mode Register (LCDM) Format ................................................................................... LCD Display Control Register (LCDC) Format ................................................................................. Relationship between LCD Display Data Memory Contents and Segment/Common Outputs ......... Common Signal Waveform ............................................................................................................... Common Signal and Segment Signal Voltages and Phases ............................................................ Example of Connection of LCD Drive Power Supply ........................................................................ 4-Time-Division LCD Display Pattern and Electrode Connections ................................................... 4-Time-Division LCD Panel Connection Example ............................................................................ 4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) ............................................... LCD Timer Control Register (LCDTM) Format ................................................................................. Sound Generator Block Diagram ...................................................................................................... Concept of Each Signal .................................................................................................................... Sound Generator Control Register (SGCR) Format ......................................................................... Sound Generator Buzzer Control Register (SGBR) Format ............................................................. Sound Generator Amplitude Register (SGAM) Format ..................................................................... Sound Generator Output Operation Timing ...................................................................................... Sound Generator Output Operation Timing ...................................................................................... Page 159 160 161 162 163 165 168 169 170 176 177 179 180 181 183 185 186 187 188 190 191 192 193 195 197 197 199 200 201 202 203 205 206 208 210 211 212 212 14-3. 14-4. 14-5. 14-6. 14-7. 14-8. 14-9. 15-1. 15-2. 15-3. 15-4. 15-5. 16-1. 16-2. 16-3. 16-4. 16-5. 16-6. 16-7. 16-8. 16-9. 16-10. 16-11. 16-12. 17-1. 17-2. 17-3. 17-4. 17-5. 17-6. 17-7. 19 LIST OF FIGURES (4/4) Figure No. 18-1. 18-2. 18-3. 18-4. 18-5. 18-6. 18-7. 18-8. www..com Title Meter Controller/Driver Block Diagram ............................................................................................. 1-Bit Addition Circuit Block Diagram ................................................................................................. Timer Mode Control Register (MCNTC) Format ............................................................................... Compare Control Register n (MCMPCn) Format .............................................................................. Port Mode Control Register (PMC) Format ...................................................................................... Restart Timing after Count Stop (Count StartCount StopCount Start) ...................................... Timing in 1-Bit Addition Circuit Operation ......................................................................................... Timing of Output with 1 Clock Shifted ............................................................................................... Basic Configuration of Interrupt Function ......................................................................................... Interrupt Request Flag Register (IF0L, IF0H, IF1L) Format .............................................................. Interrupt Mask Flag Register (MK0L, MK0H, MK1L) Format ............................................................ Priority Specify Flag Register (PR0L, PR0H, PR1L) Format ............................................................ External Interrupt Rising Edge Enable Register (EGP), External Interrupt Falling Edge Enable Register (EGN) Format ....................................................... Page 213 214 216 217 218 220 221 222 225 228 229 230 231 232 233 235 235 236 238 239 239 241 243 246 248 249 251 252 253 254 254 254 258 259 260 261 261 280 289 19-1. 19-2. 19-3. 19-4. 19-5. 19-6. 19-7. 19-8. 19-9. 19-10. 19-11. 19-12. 19-13. 19-14. 19-15. 20-1. 20-2. 20-3. 20-4. 20-5. 21-1. 21-2. 21-3. 21-4. 22-1. 22-2. 22-3. 22-4. 22-5. A-1. A-2. Prescaler Mode Register (PRM0) Format ........................................................................................ Program Status Word Format ........................................................................................................... Non-Maskable Interrupt Request Generation to Acknowledge Flowchart ........................................ Non-Maskable Interrupt Request Acknowledge Timing .................................................................... Non-Maskable Interrupt Request Acknowledge Operation ............................................................... Interrupt Request Acknowledge Processing Algorithm ..................................................................... Interrupt Request Acknowledge Timing (Minimum Time) ................................................................. Interrupt Request Acknowledge Timing (Maximum Time) ................................................................ Multiple Interrupt Examples .............................................................................................................. Interrupt Request Hold ...................................................................................................................... Oscillation Stabilization Time Select Register (OSTS) Format ......................................................... HALT Mode Clear upon Interrupt Generation ................................................................................... HALT Mode Clear upon RESET Input .............................................................................................. STOP Mode Clear upon Interrupt Generation .................................................................................. STOP Mode Clear upon RESET Input .............................................................................................. Reset Function Block Diagram ......................................................................................................... Timing of Reset by RESET Input ...................................................................................................... Timing of Reset due to Watchdog Timer Overflow ........................................................................... Timing of Reset in STOP Mode by RESET Input .............................................................................. Memory Size Switching Register (IMS) Format ................................................................................ Transmission Method Selection Format ........................................................................................... Flashpro II Connection Using 3-Wire Serial I/O Method ................................................................... Flashpro II Connection Using UART Method .................................................................................... Flashpro II Connection Using Pseudo 3-Wire Serial I/O Method ...................................................... Development Tool Configuration ....................................................................................................... Dimensions of TGF-080RAP (Reference) ........................................................................................ 20 LIST OF TABLES (1/2) Table No. 2-1. 3-1. 3-2. 3-3. 3-4. 3-5. www..com Title Pin Input/Output Circuit Types .......................................................................................................... Internal Memory Capacity ................................................................................................................. Vector Table ...................................................................................................................................... Internal High-Speed RAM Capacity .................................................................................................. Internal High-Speed RAM Area ........................................................................................................ Special Function Register List .......................................................................................................... Port Functions ................................................................................................................................... Port Configuration ............................................................................................................................. Port Mode Register and Output Latch Settings when Using Alternate Functions ............................. Clock Generator Configuration ......................................................................................................... Relation between CPU Clock and Minimum Instruction Execution Time .......................................... Maximum Time Required for Switching CPU Clock .......................................................................... Timer/Event Counter Operations ...................................................................................................... Timer 0 Configuration ....................................................................................................................... Timer 1 Configuration ....................................................................................................................... Timers 2 and 3 Configurations .......................................................................................................... Interval Timer Interval Time .............................................................................................................. Watch Timer Configuration ............................................................................................................... Interval Timer Interval Time .............................................................................................................. Watchdog Timer Runaway Detection Time ....................................................................................... Interval Time ..................................................................................................................................... Watchdog Timer Configuration ......................................................................................................... Watchdog Timer Runaway Detection Time ....................................................................................... Interval Timer Interval Time .............................................................................................................. Clock Output Control Circuit Configuration ....................................................................................... A/D Converter Configuration ............................................................................................................. UART Configuration .......................................................................................................................... Relation between 5-bit Counter's Source Clock and "n" Value ......................................................... Relation between Main System Clock and Baud Rate ..................................................................... Causes of Receive Errors ................................................................................................................. SIO3 Configuration ........................................................................................................................... Page 38 43 43 44 48 52 74 75 85 89 90 96 100 102 112 121 134 134 136 140 140 141 143 144 145 150 166 175 176 181 184 5-1. 5-2. 5-3. 6-1. 6-2. 6-3. 7-1. 7-2. 8-1. 9-1. 10-1. 10-2. 10-3. 11-1. 11-2. 11-3. 11-4. 11-5. 12-1. 13-1. 14-1. 14-2. 14-3. 14-4. 15-1. 21 LIST OF TABLES (2/2) Table No. 16-1. 16-2. 16-3. 16-4. 16-5. 16-6. 17-1. www..com Title Maximum Number of Display Pixels ................................................................................................. LCD Controller/Driver Configuration ................................................................................................. COM Signals ..................................................................................................................................... LCD Drive Voltage ............................................................................................................................ LCD Drive Voltage ............................................................................................................................ Selection and Non-Selection Voltages (COM0 to COM3) ................................................................ Sound Generator Configuration ........................................................................................................ Meter Controller/Driver Configuration ............................................................................................... Interrupt Source List ......................................................................................................................... Flags Corresponding to Interrupt Request Sources ......................................................................... Times from Generation of Maskable Interrupt Request until Servicing ............................................. Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing ...................................... HALT Mode Operating Status ........................................................................................................... Operation after HALT Mode Clear .................................................................................................... STOP Mode Operating Status .......................................................................................................... Operation after STOP Mode Clear .................................................................................................... Hardware Status after Reset ............................................................................................................ Differences between PD78F0974 and PD780973(A) ................................................................... Memory Size Switching Register Settings ........................................................................................ Transmission Method List ................................................................................................................. Main Functions of Flash Memory Programming ............................................................................... Operand Identifiers and Description Formats ................................................................................... Upgrading Former In-circuit Emulator for 78K/0 Series to IE-78001-R-A ......................................... Page 189 190 196 196 198 200 206 214 224 227 237 240 247 249 250 252 255 257 258 259 260 264 288 18-1. 19-1. 19-2. 19-3. 19-4. 20-1. 20-2. 20-3. 20-4. 21-1. 22-1. 22-2. 22-3. 22-4. 23-1. A-1. 22 CHAPTER 1 OUTLINE 1.1 Features * Internal memory Item Part Number Program Memory (ROM/Flash Memory) 24 Kbytes 32 Kbytes Internal High-Speed RAM 768 bytes 1024 bytes Data Memory LCD Display RAM 20 x 4 bits EEPROMTM 256 bytes PD780973(A) PD78F0974 www..com * * High-speed instruction execution time (0.24 s: @ 8.38-MHz operation with main system clock) Instruction set suited to system control * Bit manipulation possible in all address spaces * Multiply and divide instructions * * Fifty-six I/O ports : (including pins that have an alternate function as segment signal output) LCD controller/driver * Segment signal output : 20 max. * Common signal output : 4 max. * Bias * Power supply voltage : 1/3 bias : VLCD = 3.0 V to VDD : 2 channels : 1 channel : 1 channel : 1 channel : 1 channel : 1 channel : Can set pulse width with a precision of 8 + 1 bits with 1-bit addition function * * 8-bit resolution A/D converter : 5 channels Serial interface * UART mode * 3-wire serial I/O mode : 1 channel * Timer : Six channels * 16-bit timer * 8-bit timer * Watch timer * Watchdog timer * 8-bit timer/event counter : 2 channels * * * * Meter controller/driver : PWM output (8-bit resolution) : 16 Sound generator : 1 channel Vectored interrupt sources : 21 Power supply voltage : VDD = 5 V 10% 1.2 Applications Automobile meter (dash board) control 23 CHAPTER 1 OUTLINE 1.3 Ordering Information Part Number Package 80-pin plastic QFP (14 x 20 mm) 80-pin plastic QFP (14 x 20 mm) Internal ROM Mask ROM Flash memory PD780973GF(A)-xxx-3B9 PD78F0974GF-3B9 1.4 Quality Grade Part Number Package 80-pin plastic QFP (14 x 20 mm) 80-pin plastic QFP (14 x 20 mm) Quality Grade Standard Special PD78F0974GF-3B9 PD780973GF(A)-xxx-3B9 www..com Remark xxx indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. 24 CHAPTER 1 OUTLINE 1.5 Pin Configuration (Top View) * 80-pin plastic QFP (14 x 20 mm) PD780973GF(A)-xxx, 78F0974GF S12/P90 S11/P91 S10/P92 S9/P93 S8/P94 S7/P95 S6/P96 S5/P97 COM3 COM2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 www..com P87/S13 P86/S14 P85/S15 P84/S16 P83/S17 P82/S18 TPO/P81/S19 IC (VPP) X1 X2 VSS VDD RESET P07 P06 P05 P04 P03 INTP2/P02 INTP1/P01 INTP0/P00 AVREF P14/ANI4 P13/ANI3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 COM0 VLCD SMVSS SMVDD SM11/P20 SM12/P21 SM13/P22 SM14/P23 SM21/P24 SM22/P25 SM23/P26 SM24/P27 SM31/P30 SM32/P31 SM33/P32 SM34/P33 SM41/P34 SM42/P35 SM43/P36 SM44/P37 SMVDD SMVSS SGO/SGOF/P61 SGOA/PCL/P60 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ANI2/P12 ANI1/P11 ANI0/P10 RxD/P53 TxD/P54 TI00/P40 TI01/P41 TI02/P42 TIO2/P43 Cautions 1. Connect IC (Internally Connected) pin to VSS directly. 2. Connect AVSS pin to VSS. Remarks 1. When these devices are used in applications that require reduction of the noise generated from inside the microcontroller, the implementation of noise reduction measures, such as supplying voltage to the two VDD individually, and connecting the two VSS to different ground lines, is recommended. 2. Pin connection in parentheses is intended for the PD78F0974. TIO3/P44 SCK/P50 SO/P51 SI/P52 AVSS VDD VSS COM1 S4 S3 S2 S1 S0 25 CHAPTER 1 OUTLINE ANI0 to ANI4 AVREF AVSS IC P00 to P07 P10 to P14 P20 to P27 P30 to P37 P40 to P44 P50 to P54 www..com P61 P60, : Analog Input : Analog Reference Voltage : Analog Ground : Internally Connected : Port0 : Port1 : Port2 : Port3 : Port4 : Port5 : Port6 : Port8 : Port9 : Clock Output : Reset : Receive Data : Segment Output SCK SGO SGOA SGOF SI : Serial Clock : Sound Generator Output : Sound Generator Amplitude Output : Sound Generator Frequency Output : Serial Input : Meter Output COM0 to COM3 : Common Output INTP0 to INTP2 : Interrupt from Peripherals SM11 to SM14, SM21 to SM24, SM31 to SM34, SM41 to SM44 SMVDD SMVSS SO TI00 to TI02 TIO2, TIO3 TPO TxD VDD VLCD VPP VSS X1, X2 : Meter Controller Power Supply : Meter Controller Ground : Serial Output : Timer Input : Timer Output/Event Counter Input : Prescaler Output : Transmit Data : Power Supply : LCD Power Supply : Programming Power Supply : Ground : Crystal (Main System Clock) P81 to P87 P90 to P97 PCL RESET RxD S0 to S19 26 CHAPTER 1 OUTLINE 1.6 78K/0 Series Product Development These products are a further development in the 78K/0 Series. The designations appearing inside the boxes are subseries names. Products in mass production Products under development Y subseries products are compatible with I2C bus. Control 100-pin PD78075B PD78078 PD78070A PD780058 PD78058F PD78054 PD780034 PD780024 PD78014H PD78018F PD78014 PD780001 PD78002 PD78083 PD78078Y PD78070AY PD780018AY PD780058YNote PD78058FY PD78054Y PD780034Y PD780024Y PD78018FY PD78014Y PD78002Y EMI-noise reduced version of the PD78078. Timer was added to the PD78054, and the external interface function was enhanced. ROM-less versions of the PD78078. Serial I/O of the PD78078Y was enhanced, and only selected functions are provided. Serial I/O of the PD78054 was enhanced, EMI-noise reduced version. EMI-noise reduced version of the PD78054. UART and D/A converter were added to the PD78014, and I/O was enhanced. A/D converter of the PD780024 was enhanced. Serial I/O of the PD78018F was enhanced. EMI-noise reduced version of the PD78018F. Low-voltage (1.8 V) operation versions of the PD78014 with several ROM and RAM capacities available. A/D converter and 16-bit timer were added to the PD78002. A/D converter was added to the PD78002. Basic subseries for control. On-chip UART, capable of operating at a low voltage (1.8 V). www..com 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin Inverter control 64-pin 64-pin 64-pin PD780988 PD780964 PD780924 Inverter control, timer, and SIO of the PD780964 were enhanced, with ROM and RAM expansion. A/D converter of the PD780924 was enhanced. On-chip inverter control circuit and UART, EMI-noise reduced version. FIPTM drive 78K/0 Series 100-pin 100-pin 80-pin 80-pin PD780208 PD780228 PD78044H PD78044F I/O and FIP C/D of the PD78044F were enhanced, Display output total: 53 I/O and FIP C/D of the PD78044H were enhanced, Display output total: 48 N-ch open-drain input/output was added to the PD78044F, Display output total: 34 Basic subseries for driving FIP, Display output total: 34 LCD drive 100-pin 100-pin 100-pin PD780308 PD78064B PD78064 PD78064Y PD780308Y SIO of the PD78064 was enhanced, and ROM and RAM were expanded. EMI-noise reduced version of the PD78064. Basic subseries for driving LCDs, On-chip UART. IEBusTM supported 80-pin 80-pin PD78098B PD78098 EMI-noise reduced version of the PD78098. IEBus controller was added to the PD78054. Meter control 80-pin PD780973 On-chip automobile meter driving controller/driver. Note Under planning 27 CHAPTER 1 OUTLINE The major functional differences among the subseries are shown below. Function Subseries Name Control Timer 8-bit 4 ch 16-bit 1 ch Watch WDT 1 ch 1 ch VDD External MIN. Expansion Value 1.8 V Available ROM Capacity 8-bit 10-bit 8-bit A/D 8 ch A/D D/A - Serial Interface I/O PD78075B 32 K to 40 K PD78078 PD78070A 48 K to 60 K - 2 ch 3 ch (UART: 1 ch) 88 61 2 ch 3 ch (time-division 68 UART: 1ch) 3 ch (UART: 1 ch) 69 2.7 V 1.8 V PD780058 24 K to 60 K PD78058F 48 K to 60 K www..com 2.7 V 2.0 V PD78054 16 K to 60 K - 8 ch 8 ch - - 3 ch (UART: 1 ch, time- 51 division 3-wire: 1 ch) 2 ch 53 PD780034 8 K to 32 K PD780024 PD78014H PD78018F 8 K to 60 K PD78014 8 K to 32 K - - 1 ch - 3 ch Note 1 Note 2 - 1 ch 1.8 V 2.7 V 1 ch - 8 ch - 8 ch - 39 53 1 ch (UART: 1 ch) 33 3 ch (UART: 2 ch) 47 2 ch (UART: 2 ch) 8 ch 2 ch 3 ch 2 ch 1 ch - 1 ch 1 ch - 1 ch 2 ch 2 ch 1 ch 1 ch 1 ch 8 ch - - 3 ch (time-division 57 UART: 1 ch) 2 ch (UART: 1 ch) 2.0 V - 1 ch 8 ch - - - 2 ch 1 ch 74 72 68 2.7 V 4.5 V 2.7 V - 1.8 V - Available - PD780001 8 K PD78002 PD78083 Inverter control 8 K to 16 K PD780988 32 K to 60 K PD780964 8 K to 32 K PD780924 4.0 V Available 2.7 V FIP drive PD780208 32 K to 60 K PD780228 48 K to 60 K PD78044H 32 K to 48 K PD78044F 16 K to 40 K LCD drive PD780308 48 K to 60 K PD78064B 32 K PD78064 16 K to 32 K IEBus PD78098B 40 K to 60 K 32 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch - 2 ch 3 ch (UART: 1 ch) 69 2.7 V Available supported PD78098 Meter control PD780973 24 K to 32 K 3 ch 1 ch 1 ch 1 ch 5 ch - - 2 ch (UART: 1 ch) 56 4.5 V - Notes 1. 16-bit timer: 2 channels 10-bit timer: 1 channel 2. 10-bit timer: 1 channel 28 CHAPTER 1 OUTLINE 1.7 Block Diagram TI00/P40 to TI02/P42 16-bit TIMER0 PORT0 P00 to P07 8-bit TIMER1 8-bit TIMER/ EVENT COUNTER2 8-bit TIMER/ EVENT COUNTER3 WATCHDOG TIMER WATCH TIMER SCK/P50 SO/P51 SI/P52 RxD/P53 TxD/P54 ANI0/P10 to ANI4/P14 AVSS AVREF POWER FAIL DETECTOR INTP0/P00 to INTP2/P02 INTERRUPT CONTROL STANDBY CONTROL PCL/SGOA/P60 CLOCK OUTPUT CONTROL SOUND GENERATOR OUTPUT RAM EEPROM A/D CONVERTER SERIAL INTERFACE 78K/0 CPU CORE ROM FLASH MEMORY PORT1 P10 to P14 TIO2/P43 PORT2 P20 to P27 TIO3/P44 PORT3 P30 to P37 PORT4 P40 to P44 www..com PORT5 P50 to P54 PORT6 P60, P61 PORT8 UART PORT9 P81 to P87 P90 to P97 S0 to S4 S5/P97 to S12/P90 LCD CONTROLLER/ DRIVER S13/P87 to S18/P82 S19/P81/TPO COM0 to COM3 VLCD SM11/P20 to SM14/P23 SM21/P24 to SM24/P27 SGO/SGOF/P61 METER CONTROLLER/ DRIVER SM31/P30 to SM34/P33 SM41/P34 to SM44/P37 SMVDD SMVSS VDD VSS IC (VPP) SYSTEM CONTROL X1 X2 RESET Remarks 1. The internal ROM and RAM capacities depend on the product. 2. Memory type in parentheses is for the PD78F0974. 29 CHAPTER 1 OUTLINE 1.8 Outline of Function Part Number Item Internal memory ROM PD780973(A) 24 Kbytes (Mask ROM) 768 bytes 256 bytes 20 x 4 bits 8 bits x 32 registers (8 bits x 8 registers x 4 banks) PD78F0974 32 Kbytes (Flash memory) 1024 bytes Internal high-speed RAM EEPROM LCD display RAM General register Minimum instruction execution time Instruction set www..com 0.24 s/0.48 s/0.95 s/1.91 s/3.81 s (in operation at 8.38 MHz) * 16-bit operation * Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) * Bit manipulation (set, reset, test, and Boolean operation) I/O port (including pins shared with segment signal output) Total * CMOS input * CMOS output * CMOS input/output : : : : 56 5 16 35 A/D converter * 8-bit resolution x 5 channels * Power-fail detection function * Segment signal outputs * Common signal outputs * Bias * 3-wire serial I/O mode * UART mode * * * * : 20 max. : 4 max. : 1/3 bias only : 1 channel : 1 channel 1 channel 1 channel 2 channels 1 channel LCD controller/driver Serial interface Timer 16-bit timer : 8-bit timer : 8-bit timer/event counter : Watch timer : * Watchdog timer Meter control : 1 channel PWM output (8-bit resolution) : 16 Can set pulse width with a precision of 8 + 1 bits with 1-bit addition function 1 channel 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.04 MHz, 2.09 MHz, 4.19 MHz, 8.38 MHz (@ 8.38-MHz operation with main system clock) Maskable Non-maskable Software Internal: 16, External: 3 Internal: 1 1 VDD (SMVDD) = 5 V 10% TA = -40 to +85C 80-pin plastic QFP (14 x 20 mm) Sound generator Clock output Vectored interrupt source Power supply voltage Operating ambient temperature Package 30 CHAPTER 2 PIN FUNCTION 2.1 Pin Function List (1) Port Pins Alternate Function INTP0 to INTP2 -- Pin Name P00 to P02 P03 to P07 www..com P10 to P14 Input/Output Input/Output Function Port 0 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, an on-chip pull-up resistor can be used by software. Port 1 5-bit input only port. Port 2 8-bit output only port. After Reset Input Input Input ANI0 to ANI4 P20 to P23 P24 to P27 P30 to P33 P34 to P37 P40 to P42 P43, P44 Output Hi-Z SM11 to SM14 SM21 to SM24 Output Port 3 8-bit output only port. Hi-Z SM31 to SM34 SM41 to SM44 Input/Output Port 4 5-bit input/output port. Input/output mode can be specified bit-wise. Port 5 5-bit input/output port. Input/output mode can be specified bit-wise. Input TI00 to TI02 TIO2, TIO3 P50 P51 P52 P53 P54 P60 P61 Input/Output Input SCK SO SI RxD TxD Input/Output Port 6 2-bit input/output port. Input/output mode can be specified bit-wise. Port 8 7-bit input/output port. Input/output mode can be specified bit-wise. Can be set in I/O port mode or segment output mode in 2bit units by using LCD display control register (LCDC). Port 9 8-bit input/output port. Input/output mode can be specified bit-wise. Can be set in I/O port mode or segment output mode in 2bit units by using LCD display control register (LCDC). Input PCL/SGOA SGO/SGOF P81 P82 to P87 Input/Output Input S19/TPO S18 to S13 P90 to P97 Input/Output Input S12 to S5 31 CHAPTER 2 PIN FUNCTION (2) Non-port pins Alternate Function P00 to P02 Pin Name INTP0 to INTP2 Input/Output Input Function External interrupt request input with specifiable valid edges (rising edge, falling edge, both rising and falling edges). Serial interface serial data input. Serial interface serial data output. Serial interface serial data input/output. Asynchronous serial interface serial data input. Asynchronous serial interface serial data output. input to capture register (CR00). t Capture trigger signal m 4U.co Capture trigger signal input to capture register (CR01). Capture trigger signal input to capture register (CR02). After Reset Input SI SO SCK RxD TxD w w w . TI00 Da TI01 TI02 TIO2 TIO3 PCL SGOA SGOF SGO TPO S0 to S4 S5 to S12 S13 to S18 S19 COM0 to COM3 VLCD SM11 to SM14 SM21 to SM24 SM31 to SM34 SM41 to SM44 ANI0 to ANI4 AVREF t a S Input Output Input/Output Input Output hInput e e Input Input Input Input Input Input P52 P51 P50 P53 P54 P40 P41 P42 Input/Output 8-bit timer (TM2) input/output. 8-bit timer (TM3) input/output. Input P43 P44 Output Output Clock output (for main system clock trimming). Sound generator signal output. Input Input SGOA/P60 PCL/P60 SGO/P61 SGOF/P61 Output Output Prescaler output of 16-bit timer (TM0). Segment signal output of LCD controller/driver. Input Output Input P81/S19 -- P97 to P90 P87 to P82 P81/TPO Output -- Output Common signal output of LCD controller/driver. LCD driving power supply. Meter control signal output. Output -- Hi-Z -- -- P20 to P23 P24 to P27 P30 to P33 P34 to P37 Input Input A/D converter analog input. A/D converter reference voltage input (shared with analog power supply). A/D converter ground potential. Same potential as VSS. System reset input. Crystal connection for main system clock oscillation. Input -- P10 to P14 -- AVSS RESET X1 X2 SMVDD SMVSS VDD VSS VPP -- Input Input -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Power supply for meter controller/driver. Ground potential for meter controller/driver. Positive power supply. Ground potential. High-voltage application for program write/verify. Connect directly to VSS in normal operating mode. Internally connected. Connect directly to VSS. -- -- -- -- -- IC -- -- -- 32 CHAPTER 2 PIN FUNCTION 2.2 Description of Pin Functions 2.2.1 P00 to P07 (Port 0) These pins constitute an 8-bit input/output port. In addition, they are also used to input external interrupt request signals. The following operating modes can be specified bit-wise. (1) Port mode In this mode, P00 to P07 function as an 8-bit input/output port. P00 to P07 can be specified as an input or output port bit-wise with port mode register 0 (PM0). When these pins are used as an input port, an on-chip pull-up resistor can be used if so specified by the pull-up resistor option register (PU0). www..com (2) Control mode In this mode, P00 to P07 function as external interrupt input pins (INTP0 to INTP2) and external interrupt request input pins with specifiable valid edges (rising edge, falling edge, both rising and falling edges). 2.2.2 P10 to P14 (Port 1) These pins constitute a 5-bit input only port. In addition, they are also used to input A/D converter analog signals. The following operating modes can be specified bit-wise. (1) Port mode In this mode, P10 to P14 function as a 5-bit input only port. (2) Control mode In this mode, P10 to P14 function as A/D converter analog input pins (ANI0 to ANI4). 2.2.3 P20 to P27 (Port 2) These pins constitute an 8-bit output only port. In addition, they are also used as PWM output pins to control meters. The following operating modes can be specified bit-wise. (1) Port mode In this mode, P20 to P27 function as an 8-bit output only port. They go into a high-impedance state when 1 is set to port mode register 2 (PM2). (2) Control mode In this mode, P20 to P27 function as PWM output pins (SM11 to SM14 and SM21 to SM24) for meter control. 33 CHAPTER 2 PIN FUNCTION 2.2.4 P30 to P37 (Port 3) These pins constitute an 8-bit output only port. In addition, they also function as PWM output pins to control meters. The following operating modes can be specified bit-wise. (1) Port mode In this mode, P30 to P37 function as an 8-bit output only port. They go into a high-impedance state when 1 is set to port mode register 3 (PM3). (2) Control mode In this mode, P30 to P37 function as PWM output pins (SM31 to SM34 and SM41 to SM44) for meter control. 2.2.5 P40 to P44 (Port 4) www..com pins constitute a 5-bit input/output port. In addition, they also function as timer input/output pins. These The following operating modes can be specified bit-wise. (1) Port mode In this mode, P40 to P44 function as a 5-bit input/output port. They can be set bit-wise in the input or output mode by using port mode register 4 (PM4). (2) Control mode In this mode, P40 to P44 function as timer input/output pins. (a) TIO2, TIO3 Timer output pins. (b) TI00 to TI02 These pins input a capture trigger signal to the 16-bit timer capture registers (CR00 to CR02). 2.2.6 P50 to P54 (Port 5) These pins constitute a 5-bit input/output port. In addition, they also function as serial interface data input/output and clock input/output pins. The following operating modes can be specified bit-wise. (1) Port mode In this mode, P50 to P54 function as a 5-bit input/output port. They can be set bit-wise in the input or output mode by using port mode register 5 (PM5). (2) Control mode In this mode, P50 to P54 function as serial interface data input/output and clock input/output. (a) SI Serial interface serial data input pin. (b) SO Serial interface serial data output pin. 34 CHAPTER 2 PIN FUNCTION (c) SCK Serial interface serial clock input/output pin. (d) RxD, TxD Asynchronous serial interface serial data input/output pins. 2.2.7 P60, P61 (Port 6) These pins constitute a 2-bit input/output port. In addition, they also function as clock output and sound generator output pins. The following operating modes can be specified bit-wise. (1) Port mode www..com In this mode, P60 and P61 function as a 2-bit input/output port. They can be set bit-wise in the input or output mode by using port mode register 6 (PM6). (2) Control mode In this mode, P60 and P61 function as clock output and sound generator output pins. (a) PCL Clock output pin. (b) SGOF Sound generator (without amplitude) signal output pin. (c) SGO Sound generator (with amplitude) signal output pin. (d) SGOA Sound generator amplitude signal output pin. 2.2.8 P81 to P87 (Port 8) These pins constitute a 7-bit input/output port. In addition, they also function as output pins for segment signals from the internal LCD controller/driver, and one of them as a prescaler signal output pin. The following operating modes can be specified bit-wise. (1) Port mode In this mode, P81 to P87 function as a 7-bit input/output port. They can be set bit-wise in the input or output mode by using port mode register 8 (PM8). (2) Control mode In this mode, P81 to P87 function as segment signal output pins of the LCD controller/driver, and one of them as a prescaler signal output pins. (a) S13 to S19 Segment signal output pins of the LCD controller/driver. (b) TPO Prescaler signal output pin of the 16-bit timer. 35 CHAPTER 2 PIN FUNCTION 2.2.9 P90 to P97 (Port 9) These pins constitute an 8-bit input/output port. In addition, they also function to output segment signals from the internal LCD controller/driver. The following operating modes can be specified bit-wise. (1) Port mode In this mode, P90 to P97 function as an 8-bit input/output port. They can be set bit-wise in the input or output mode by using port mode register 9 (PM9). (2) Control mode In this mode, P90 to P97 function as segment signal output pins (S5 to S12) of the LCD controller/driver. www..com COM0 to COM3 2.2.10 These pins output common signals from the internal LCD controller/driver during 4-time division drive in 1/3 bias mode (COM0 to COM3 outputs). 2.2.11 VLCD This pin supplies a voltage to drive an LCD. 2.2.12 AVREF This is an A/D converter reference voltage input pin. This pin also functions as an analog power supply pin. Supply power to this pin when the A/D converter is used. When A/D converter is not used, connect this pin to VSS. 2.2.13 AVSS This is a ground voltage pin of A/D converter. Always use the same voltage as that of the VSS pin even when an A/D converter is not used. 2.2.14 RESET This is a low-level active system reset input pin. 2.2.15 X1 and X2 Crystal resonator connect pins for main system clock oscillation. When using an external clock supply, input it to X1 and its inverted signal to X2. 2.2.16 SMVDD This pin supplies a positive power to the meter controller/driver. 2.2.17 SMVSS This is the ground pin of the meter controller/driver. 2.2.18 VDD Positive power supply port pin. 2.2.19 VSS Ground potential port pin. 36 CHAPTER 2 PIN FUNCTION 2.2.20 VPP (PD78F0974) A high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified. Directly connect this pin to VSS in the normal operating mode. 2.2.21 IC (PD780973(A)) The IC (Internally Connected) pin is provided to set the test mode to check the PD780973(A) before shipment. In the normal operating mode, directly connect this pin to the VSS pin with as short a wiring length as possible. When a potential difference is generated between the IC pin and VSS pin because the wiring between those two pins is too long or external noise is input to the IC pin, the user's program may not run normally. * Directly connect the IC pin to the VSS pin. www..com VSS IC Keep short 37 CHAPTER 2 PIN FUNCTION 2.3 Input/output Circuits and Recommended Connection of Unused Pins Table 2-1 shows the input/output circuit types of pins and the recommended connection for unused pins. Refer to Figure 2-1 for the configuration of the input/output circuit of each type. Table 2-1. Pin Input/Output Circuit Types Pin Name P00/INTP0 P01/INTP1 P02/INTP2 P03 to P07 www..com P10/ANI0 to P14/ANI4 P20/SM11 to P23/SM14 P24/SM21 to P27/SM24 P30/SM31 to P33/SM34 P34/SM41 to P37/SM44 P40/TI00 to P42/TI02 P43/TIO2 P44/TIO3 P50/SCK P51/SO P52/SI P53/RxD P54/TxD P60/SGOA/PCL P61/SGO/SGOF P81/S19/TPO P82/S18 to P87/S13 P90/S12 to P97/S5 S0 to S4 COM0 to COM3 VLCD RESET SMVDD SMVSS AVREF AVSS VPP (PD78F0974) IC (PD780973(A)) Connect directly to VSS. 17 18 -- 2 -- -- Input -- Connect to VDD. Connect to VSS. -- Output Leave open. 17-G 5 5 8 8 Input/output Independently connect to VDD or VSS via a resistor. Input/Output Circuit Type 8-A Input/Output Input/output Recommended Connection of Unused Pins Independently connect to VSS via a resistor. 9 4 Input Output Independently connect to VDD or VSS via a resistor. Leave open. 38 CHAPTER 2 PIN FUNCTION Figure 2-1. I/O Circuits of Pins (1/2) Type 2 Type 8 VDD data IN output disable N-ch P-ch IN/OUT www..com Schmitt-triggered input with hysteresis characteristics Type 4 Type 8-A VDD VDD data P-ch OUT output disable pullup enable data P-ch VDD P-ch IN/OUT N-ch output disable N-ch Push-pull output whose output can go into a highimpedance state (both P-ch and N-ch are off). Type 5 VDD data P-ch IN/OUT output disable N-ch IN P-ch N-ch + - Type 9 Comparator VREF (Threshold voltage) input enable input enable 39 CHAPTER 2 PIN FUNCTION Figure 2-1. I/O Circuits of Pins (2/2) Type 17 Type 17-G VLC0 VLC1 P-ch N-ch SEG data P-ch VLC2 www..com VDD P-ch OUT N-ch output disable N-ch data P-ch IN/OUT N-ch input enable VLC0 P-ch VLC1 VLC0 P-ch VLC1 N-ch P-ch N-ch OUT VLC2 N-ch P-ch VLC2 N-ch SEG data N-ch COM data N-ch P-ch P-ch N-ch P-ch Type 18 40 CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Spaces The PD780973 Subseries can access a 64-Kbyte memory space. Figures 3-1 and 3-2 show memory maps of the respective devices. Figure 3-1. Memory Map (PD780973(A)) FFFFH Special Function Registers (SFRs) 256 x 8 bits General Registers 32 x 8 bits www..com FF00H FEFFH FEE0H FEDFH Internal High-speed RAM 768 x 8 bits FC00H FBFFH FA6DH FA6CH LCD Display RAM 20 x 4 bits Data memory space FA59H FA58H Reserved FA00H F9FFH EEPROM 256 x 8 bits F900H F8FFH Reserved 6000H 5FFFH Program memory space 0080H 007FH CALLT Table Area Internal ROM 24576 x 8 bits 0040H 003FH Vector Table Area 0000H 0000H 0800H 07FFH Program Area 5FFFH Program Area 1000H 0FFFH CALLF Entry Area Reserved 41 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map (PD78F0974) FFFFH FF00H FEFFH FEE0H FEDFH Special Function Registers (SFRs) 256 x 8 bits General Registers 32 x 8 bits Internal High-speed RAM 1024 x 8 bits FB00H FAFFH www..com Reserved FA6DH FA6CH LCD Display RAM 20 x 4 bits 7FFFH Program Area 1000H 0FFFH CALLF Entry Area EEPROM 256 x 8 bits F900H F8FFH Reserved 8000H 7FFFH Program memory space 0080H 007FH CALLT Table Area Flash Memory 32768 x 8 bits 0040H 003FH Vector Table Area 0000H 0000H 0800H 07FFH Program Area Data memory space FA59H FA58H Reserved FA00H F9FFH 42 CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space contains the program and table data. Normally, it is addressed with the program counter (PC). The PD780973 Subseries incorporate internal ROM (or flash memory), as listed below. Table 3-1. Internal Memory Capacity Part Number Type Mask ROM Flash Memory Capacity 24576 x 8 bits (0000H to 5FFFH) 32768 x 8 bits (0000H to 7FFFH) PD780973(A) PD78F0974 The following three areas are allocated to the program memory space. www..com (1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. This area stores program start addresses to which execution branches when the RESET signal is input or when an interrupt request is generated. Of a 16-bit address, the lower 8 bits are stored at an even address and the higher 8 bits are stored at an odd address. Table 3-2. Vector Table Vector Table Address 0000H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H 0022H 0024H 0026H 0028H 003EH Interrupt Source RESET input INTWDT INTAD INTOVF INTTM00 INTTM01 INTTM02 INTP0 INTP1 INTP2 INTCS10 INTSER INTSR INTST INTTM1 INTTM2 INTTM3 INTWE INTWI INTWT BRK 43 CHAPTER 3 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF). 3.1.2 Internal data memory space The PD780973 Subseries have the following RAM. (1) Internal high-speed RAM Table 3-3. Internal High-Speed RAM Capacity www..com Product Internal High-Speed RAM 768 x 8 bits (FC00H to FEFFH) 1024 x 8 bits (FB00H to FEFFH) PD780973(A) PD78F0974 The 32-byte area FEE0H to FEFFH is allocated with four general-purpose register banks composed of eight 8bit registers. The internal high-speed RAM can be used as stack memory. (2) LCD display RAM An LCD display RAM is allocated to a 20 x 4 bits area consisting of FA59H to FA6CH. The LCD display RAM can also be used as a normal RAM. 3.1.3 Special function register (SFR) area An on-chip peripheral hardware special-function register (SFR) is allocated in the area FF00H to FFFFH (Refer to 3.2.3 Special function registers (SFRs) Table 3-5 Special Function Register List). Caution Do not access addresses where the SFR is not assigned. 44 CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. The address of an instruction to be executed next is addressed by the program counter (PC) (for details, see 3.3 Instruction Address Addressing). Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the PD780973 Subseries, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of special function registers (SFR) and generalpurpose registers are available for use. Data memory addressing is illustrated in Figures 3-3 and 3-4. For the details of each addressing mode, see 3.4 Operand Address Addressing. Figure 3-3. Data Memory Addressing (PD780973(A)) www..com FFFFH Special Function Registers (SFRs) 256 x 8 bits SFR Addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General Registers 32 x 8 bits Internal High-speed RAM 768 x 8 bits Register Addressing Short Direct Addressing FE20H FE1FH FC00H FBFFH Reserved FA6DH FA6CH LCD Display RAM 20 x 4 bits FA59H FA58H Reserved FA00H F9FFH EEPROM 256 x 8 bits F900H F8FFH Reserved 6000H 5FFFH Internal ROM 24576 x 8 bits 0000H Direct Addressing Register Indirect Addressing Based Addressing Based Indexed Addressing 45 CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Data Memory Addressing (PD78F0974) FFFFH FF20H FF1FH FF00H FEFFH FEE0H FEDFH Special Function Registers (SFRs) 256 x 8 bits SFR Addressing General Registers 32 x 8 bits Internal High-speed RAM 1024 x 8 bits Register Addressing Short Direct Addressing FE20H FE1FH www..com FB00H FAFFH Reserved FA6DH FA6CH LCD Display RAM 20 x 4 bits FA59H FA58H Reserved FA00H F9FFH EEPROM 256 x 8 bits F900H F8FFH Reserved 8000H 7FFFH Flash Memory 32768 x 8 bits 0000H Direct Addressing Register Indirect Addressing Based Addressing Based Indexed Addressing 46 CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The PD780973 Subseries incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, status, and stack memory. The control registers consist of a program counter, a program status word, and a stack pointer. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set. www..com RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 3-5. Program Counter Configuration 15 0 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically reset upon execution of the RETB, RETI and POP PSW instructions. RESET input sets the PSW to 02H. Figure 3-6. Program Status Word Configuration 7 PSW IE Z RBS1 AC RBS0 0 ISP 0 CY 47 CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE is set to DI, and only non-maskable interrupt request becomes acknowledgeable. Other interrupt requests are all disabled. When 1, the IE is set to EI and interrupt request acknowledge enable is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources and a priority specify flag. The IE is reset (to 0) upon DI instruction execution or interrupt acknowledgement and is set (to 1) upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set (to 1). It is reset (to 0) in all other cases. www..com Register bank select flags (RBS0 and RBS1) (c) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information which indicates the register bank selected by SEL RBn instruction execution is stored. (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (to 1). It is reset (to 0) in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, lowlevel vectored interrupts specified with a priority specify flag register (PR0L, PR0H, PR1L) (refer to 19.3 (3) Priority specify flag registers (PR0L, PR0H, PR1L)) are disabled for acknowledgement. acknowledgement is controlled with the interrupt enable flag (IE). (f) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. The internal high-speed RAM areas of each product are as follows. Table 3-4. Internal High-Speed RAM Area Product Internal High-Speed RAM Area FC00H to FEFFH FB00H to FEFFH Actual PD780973(A) PD78F0974 48 CHAPTER 3 CPU ARCHITECTURE Figure 3-7. Stack Pointer Configuration 15 0 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented prior to write (save) to the stack memory and is incremented after read (restore) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-8 and 3-9. Caution Since RESET input makes SP contents undefined, be sure to initialize the SP before instruction execution. www..com Figure 3-8. Data to be Saved to Stack Memory Interrupt and BRK Instruction SP SP SP _ 2 SP _ 2 SP _ 1 SP Register Pair, Low Register Pair, High SP SP _ 2 SP _ 2 SP _ 1 SP PC7 to PC0 PC15 to PC8 SP _ 3 SP _ 3 SP _ 2 SP _ 1 SP PUSH rp Instruction CALL, CALLF, and CALLT Instructions PC7 to PC0 PC15 to PC8 PSW Figure 3-9. Data to be Reset from Stack Memory RETI and RETB Instructions POP rp Instruction RET Instruction SP SP + 1 SP SP + 2 Register Pair, Low Register Pair, High SP SP SP + 1 SP + 2 PC7 to PC0 PC15 to PC8 SP SP + 1 SP + 2 SP SP + 3 PC7 to PC0 PC15 to PC8 PSW 49 CHAPTER 3 CPU ARCHITECTURE 3.2.2 General registers General registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. Four banks of general registers, each consisting of eight 8-bit registers (X, A, C, B, E, D, L and H) are available. Each register can also be used as an 8-bit register. Two 8-bit registers can be used in pairs as a 16-bit register (AX, BC, DE and HL). They can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE and HL) and absolute names (R0 to R7 and RP0 to RP3). Register banks to be used for instruction execution are set with the CPU control instruction (SEL RBn). Because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupt processing for each bank. Figure 3-10. General Register Configuration www..com (a) Absolute Name 16-Bit Processing FEFFH R7 BANK0 FEF8H RP3 R6 R5 BANK1 FEF0H RP1 R2 R1 BANK3 FEE0H 15 0 7 0 RP0 R0 RP2 R4 R3 BANK2 FEE8H 8-Bit Processing (b) Function Name 16-Bit Processing FEFFH H BANK0 FEF8H HL L D BANK1 FEF0H BC C A BANK3 FEE0H 15 0 7 0 AX X DE E B BANK2 FEE8H 8-Bit Processing 50 CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike the general registers, these registers have special functions. They are allocated in the FF00H to FFFFH area. The special-function registers can be manipulated like the general registers, with the operation, transfer and bit manipulation instructions. The bit units (1, 8, or 16 bits) for the manipulation vary for each register. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Describe the symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address. * 8-bit manipulation Describe the symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr). www..com This manipulation can also be specified with an address. * 16-bit manipulation Describe the symbol reserved with assembler for the 16-bit manipulation instruction operand (sfrp). When addressing an address, describe an even address. Table 3-5 gives a list of special-function registers. The meaning of items in the table is as follows. * Symbol Symbol indicating the address of a special function register. It is a reserved word in the RA78K/0, and is defined via the header file "sfrbit.h" in the CC78K/0. It can be described as an instruction operand when the RA78K/ 0 and ID78K0 are used. * R/W Indicates whether the corresponding special-function register can be read or written. R/W : Read/write enable R W : Read only : Write only * Manipulatable bit units Indicates the manipulatable bit unit (1, 8, or 16). "--" indicates a bit unit for which manipulation is not possible. * After reset Indicates each register status upon RESET input. 51 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (1/3) Address FF00H FF01H FF02H FF03H FF04H FF05H FF06H FF08H www..com FF09H FF0AH FF0BH FF0CH FF0DH FF0EH FF0FH FF10H FF11H FF12H FF13H FF14H FF15H FF16H FF17H FF18H FF19H Serial I/O shift register Transmit shift register Receive buffer register FF1BH A/D conversion result register SIO TXS RXB ADCR1 R/W W R R -- -- -- -- -- -- -- -- 00H FFH FFH 00H 16-bit timer register TM0 -- -- Capture register 02 CR02 -- -- Capture register 01 CR01 -- -- Special-Function Register (SFR) Name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 8 Port 9 8-bit compare register 1 8-bit compare register 2 8-bit compare register 3 8-bit counter 1 8-bit counter 2 8-bit counter 3 Capture register 00 Symbol P0 P1 P2 P3 P4 P5 P6 P8 P9 CR1 CR2 CR3 TM1 TM2 TM3 CR00 R -- -- -- -- -- -- -- -- R/W R/W R/W R R/W Note -- Manipulatable Bit Unit 1 bit 8 bits 16 bits -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000H 00H After Reset Note When PM2 and PM3 are set to 00H, read operation is enabled. Moreover, when PM2 and PM3 are set to FFH, these ports go into a high-impedance state. 52 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (2/3) Address FF20H FF22H FF23H FF24H FF25H FF26H FF28H www..com FF29H FF30H FF40H FF41H FF42H FF48H FF49H FF4AH FF61H FF62H FF63H FF64H FF65H FF66H FF67H FF68H FF69H FF6AH FF6BH FF6CH FF6DH FF6EH FF70H FF71H FF72H FF73H FF74H FF75H Special-Function Register (SFR) Name Port mode register 0 Port mode register 2 Port mode register 3 Port mode register 4 Port mode register 5 Port mode register 6 Port mode register 8 Port mode register 9 Pull-up resistor option register Clock output selection register Watch timer mode control register Watchdog timer clock select register External interrupt rising edge enable register External interrupt falling edge enable register LCD timer control register Compare register (sin side) Compare register (cos side) Compare register (sin side) Compare register (cos side) Compare register (sin side) Compare register (cos side) Compare register (sin side) Compare register (cos side) Timer mode control register Port mode control register Compare control register 1 Compare control register 2 Compare control register 3 Compare control register 4 Prescaler mode register Capture pulse control register 16-bit timer mode control register Timer clock select register 1 Timer clock select register 2 Timer clock select register 3 Symbol PM0 PM2 PM3 PM4 PM5 PM6 PM8 PM9 PU0 CKS WTM WDCS EGP EGN LCDTM MCMP10 MCMP11 MCMP20 MCMP21 MCMP30 MCMP31 MCMP40 MCMP41 MCNTC PMC MCMPC1 MCMPC2 MCMPC3 MCMPC4 PRM0 CRC0 TMC0 TCL1 TCL2 TCL3 -- -- -- W R/W R/W R/W Manipulatable Bit Unit 1 bit 8 bits 16 bits -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 00H FFH After Reset 53 CHAPTER 3 CPU ARCHITECTURE Table 3-5. Special Function Register List (3/3) Address FF76H FF77H FF78H FF80H FF81H FF82H FF83H FF84H www..com FF85H FF86H FF87H FF89H FF90H FF94H FF95H FF96H FFA0H FFB0H FFB2H FFE0H FFE1H FFE2H FFE4H FFE5H FFE6H FFE8H FFE9H FFEAH FFF0H FFF9H FFFAH FFFBH Special-Function Register (SFR) Name 8-bit timer mode control register 1 8-bit timer mode control register 2 8-bit timer mode control register 3 A/D converter mode register Analog input channel specification register Power-fail compare mode register Power-fail compare threshold value register Serial operation mode register Asynchronous serial interface mode register Asynchronous serial interface status register Baud rate generator control register D/A converter mode register EEPROM write control register Sound generator control register Sound generator buzzer control register Sound generator amplitude register Oscillator mode register Note 1 LCD display mode register LCD display control register Interrupt request flag register 0L Interrupt request flag register 0H Interrupt request flag register 1L Interrupt mask flag register 0L Interrupt mask flag register 0H Interrupt mask flag register 1L Priority specify flag register 0L Priority specify flag register 0H Priority specify flag register 1L Memory size switching register Watchdog timer mode register Oscillation stabilization time select register Processor clock control register PR1L IMS WDTM OSTS PCC -- -- MK1L PR0 PR0L PR0H -- -- -- -- -- CFH Note 2 00H 04H IF1L MK0 MK0L MK0H -- Symbol TMC1 TMC2 TMC3 ADM1 ADS1 PFM PFT CSIM ASIM ASIS BRGC DAM1 EEWC SGCR SGBR SGAM OSCM LCDM LCDC IF0 IF0L IF0H -- FFH R R/W W R/W -- -- R/W R/W Manipulatable Bit Unit 1 bit 8 bits 16 bits -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 00H 04H After Reset Notes 1. PD780973(A) only 2. The initial value of this register is CFH. Set the following value to this register of each model. PD780973(A): 06H PD78F0974 (to set the same memory map as PD780973(A)): 06H 54 CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing (For details of instructions, refer to 78K/0 SERIES USER'S MANUAL Instructions (U12326E)). 3.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the www..com start address of the following instruction is transferred to the program counter (PC) and branched. The displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. In other words, relative addressing consists in relative branching from the start address of the following instruction to the -128 to +127 range. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Operation] 15 PC + 15 8 7 S jdisp8 15 PC 6 0 ... PC indicates the start address of the instruction after the BR instruction. 0 0 When S = 0, all bits of are 0. When S = 1, all bits of are 1. 55 CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11 instruction is branched to the 0800H to 0FFFH area. [Operation] In the case of CALL !addr16 and BR !addr16 instructions 7 www..com 0 CALL or BR Low Addr. High Addr. 15 PC 87 0 In the case of CALLF !addr11 instruction 76 fa10-8 fa7-0 4 3 CALLF 0 15 PC 0 0 0 0 11 10 1 87 0 56 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed. This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to the entire memory space. [Operation] 7 www..com Operation Code 1 6 1 5 ta4-0 1 0 1 15 Effective Address 0 0 0 0 0 0 0 8 0 7 0 6 1 5 10 0 7 Memory (Table) Low Addr. 0 Effective Address+1 High Addr. 15 PC 8 7 0 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Operation] 7 rp A 0 7 X 0 15 PC 8 7 0 57 CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general register is automatically (implicitly) addressed. Of the PD780973 Subseries instruction words, the following instructions employ implied addressing. www..com Instruction MULU DIVUW ADJBA/ADJBS ROR4/ROL4 Register to be Specified by Implied Addressing Register A for multiplicand and register AX for product storage Register AX for dividend and quotient storage Register A for storage of numeric values subject to decimal adjustment Register A for storage of digit data subject to digit rotation [Operand format] Because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [Description example] In the case of MULU X With an 8-bit x 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example, the A and AX registers are specified by implied addressing. 58 CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general register to be specified is accessed as an operand with the register specify code (Rn and RPn) in an operation code and with the register bank select flags (RBS0 and RBS1). Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [Operand format] Identifier r www..com rp Description X, A, C, B, E, D, L, H AX, BC, DE, HL `r' and `rp' can be described with function names (X, A, C, B, E, D, L, H, AX, BC, DE and HL) as well as absolute names (R0 to R7 and RP0 to RP3). [Description example] MOV A, C; when selecting C register as r Operation code 01100010 Register specify code INCW DE; when selecting DE register pair as rp Operation code 10000100 Register specify code 59 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is addressed with immediate data in an instruction word becoming an operand address. [Operand format] Identifier addr16 Description Label or 16-bit immediate data [Description example] www..com MOV A, !0FE00H; when setting !addr16 to FE00H Operation code 10001110 00000000 11111110 OP code 00H FEH [Operation] 7 OP code addr16 (lower) addr16 (upper) 0 Memory 60 CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. An internal high-speed RAM and a specialfunction register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. If the SFR area (FF00H to FF1FH) where short direct addressing is applied, ports which are frequently accessed in a program and a compare register of the timer/event counter and a capture register of the timer/event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. Refer to [Operation] below. www..com [Operand format] Identifier saddr saddrp Description Label or FE20H to FF1FH immediate data Label or FE20H to FF1FH immediate data (even address only) [Description example] MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H Operation code 00010001 00110000 01010000 [Operation] 7 OP code saddr-offset 0 OP code 30H (saddr-offset) 50H (immediate data) Short Direct Memory 15 Effective Address 1 1 1 1 1 1 1 87 0 When 8-bit immediate data is 20H to FFH, = 0 When 8-bit immediate data is 00H to 1FH, = 1 61 CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special-function register (SFR) addressing [Function] The memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing. [Operand format] Identifier sfr www..com sfrp Description Special-function register name 16-bit manipulatable special-function register name (even address only) [Description example] MOV PM0, A; when selecting PM0 (FF20H) as sfr Operation code 11110110 00100000 [Operation] 7 OP code sfr-offset 0 OP code 20H (sfr-offset) SFR 15 Effective Address 1 1 1 1 1 1 1 87 1 0 62 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] This addressing is to address a memory area to be manipulated by using as an operand address the contents of a register pair specified by the register bank select flags (RBS0 and RBS1) and the register pair specification code in the operation code. This addressing can be carried out for all the memory spaces. [Operand format] Identifier -- [DE], [HL] Description www..com [Description example] MOV A, [DE]; when selecting [DE] as register pair Operation code [Operation] 16 DE D 87 E The memory address specified with the register pair DE 0 10000101 7 The contents of the memory addressed are transferred. 7 A 0 Memory 0 63 CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in an instruction word of the register bank specified with the register bank select flags (RBS0 and RBS1) and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Identifier -- www..com [HL + byte] Description [Description example] MOV A, [HL + 10H]; when setting byte to 10H Operation code 10101110 00010000 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in an instruction word of the register bank specified with the register bank select flags (RBS0 and RBS1) and the sum is used to address the memory. Addition is performed by expanding the B or C register contents as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Identifier -- [HL + B], [HL + C] Description [Description example] In the case of MOV A, [HL + B] Operation code 10101011 64 CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and RETURN instructions are executed or the register is saved/reset upon generation of an interrupt request. Stack addressing enables to address the internal high-speed RAM area only. [Description example] In the case of PUSH DE Operation code www..com 10110101 65 [MEMO] www..com 66 CHAPTER 4 EEPROM 4.1 EEPROM Functions The PD780973 Subseries products contain on-chip 256 x 8-bit EEPROM (Electrically Erasable PROM) in addition to internal high-speed RAM, as data memory. EEPROM differs from ordinary RAM in that its contents are saved even after power is cut off. Moreover, unlike EPROM, its contents can be erased electrically without using UV light. For this reason, it is suitable for applications where the setting values of the odometer and trip meter on the dash board are saved, etc. EEPROM can be manipulated with 8-bit memory manipulation instructions. The EEPROM contained on-chip in the PD780973 Subseries has the following features. www..com (1) Written contents are saved even when the power is cut off. (2) Can be manipulated with 8-bit memory manipulation instructions in the same way as ordinary RAM. (3) Erasure and writing is performed in the time set with EWCS0 and EWCS1 (EEPROM write control register (EEWC) bits 4 and 5) (see Figure 4-2). Therefore, the write time control software load is reduced. Moreover, during writing, instructions other than instructions related to EEPROM writing and reading can also be executed. * Rewrite frequency for all chips : 1,000,000 times * Rewrite frequency per 1 byte : 100,000 times Caution The values shown above are target values. These values are subject to change without notice, so please contact your NEC sales representative for the latest value before designing. (4) When write is completed, interrupt request signal (INTWE) is issued. (5) The write enabled/disabled status can be checked with EWST (EEPROM write control register (EEWC) bit 1). 67 CHAPTER 4 EEPROM 4.2 EEPROM Configuration EEPROM is composed of EEPROM itself and a control area. The control area consists of the EEPROM write control register (EEWC) that controls EEPROM writing, and an area that generates an interrupt request signal (INTWE) upon detecting write termination. Figure 4-1. EEPROM Block Diagram Internal bus EEPROM write control register (EEWC) www..com Data latch EWCS1 EWCS0 EWCC EWST EWE EEPROM timer Prescaler fX Address latch EEPROM (256 x 8 bits) Read/write controller Write termination INTWE 68 CHAPTER 4 EEPROM 4.3 EEPROM Control Register EEPROM is controlled with the EEPROM write control register (EEWC). EEWC is set with either a 1-bit or 8-bit memory manipulation instruction. RESET input sets EEWC to 00H. Figure 4-2. EEPROM Write Control Register (EEWC) Format Address: FF90H After Reset : 00H Symbol EEWC www..com 7 0 EWCS1 0 0 Other than above 6 0 EWCS0 0 1 (214 (215 + 210)/fX Note 1 R/W 5 EWCS1 4 EWCS0 3 0 2 EWCC 1 EWST 0 EWE EEPROM Write Time + 211)/fX Note 2 Setting prohibited EWCC 0 1 Operating mode EEPROM stop EEPROM Operation Control EWST 0 EEPROM Write Status Not currently writing to EEPROM (EEPROM write/read is enabled. However, when EWE = 0, write is disabled) Currently writing to EEPROM (EEPROM write/read is disabled) 1 EWE 0 1 EEPROM write disabled EEPROM write enabled EEPROM Write Operation Control Notes 1. Set the main system clock frequency (fX) in the range of 4 to 5.120 MHz. 2. Set the main system clock frequency (fX) in the range of 5.364 to 8.38 MHz. Cautions 1. If the main system clock frequency is set in the range of 5.120 < fX < 5.364 MHz, the EEPROM cannot be used. 2. When EWE is cleared (to 0) during EEPROM writing, writing is immediately interrupted. Data that was being written becomes undefined. Be sure to clear EWE before stopping the main system clock during the write period. 3. After EWCC is cleared (to 0), set a wait time of 20 s or more by software to read EEPROM contents. 4. Be sure to check that EWST is 0 before performing EEPROM access. 5. Bits 3, 6, and 7 must be set to 0. 69 CHAPTER 4 EEPROM 4.4 EEPROM Reading Reading of EEPROM data is performed with the following procedure. <1> Check that EWST (EEPROM write control register (EEWC) bit 1) is 0 (EEPROM writing is not in progress). <2> Execute read instruction. Cautions 1. Before reading, be sure to check that EWST is 0. If an EEPROM read instruction is executed during EEPROM write, read values are undefined. 2. If reading EEPROM contents immediately after changing EWCC (EEPROM write control register (EEWC) bit 2) from 1 to 0, set a wait time of at least 20 s by software. www..com If no wait time is set, the correct values cannot be read. Example: Insertion of NOP instructions to set wait time of 20 s or more. CLR1 EWCC NOP NOP MOV A,!0F800H Insert NOP instructions to secure a wait time of 20 s or more. 70 CHAPTER 4 EEPROM 4.5 EEPROM Writing Data writing to EEPROM is performed with the following procedure. <1> Check that EWST (EEPROM write control register (EEWC) bit 1) is 0 (EEPROM writing is not in progress). <2> Set the write time with EWCS0 and EWCS1 (EEWC bits 4 and 5). <3> Set EWE (EEWC bit 0) to 1 (EEPROM writing enabled). <4> Execute write instruction. If performing several write operations in succession, perform the next write operation after the current write operation has been completed. The following methods can be used for write termination and time control. www..com (1) Method using write termination interrupt request (INTWE) After writing 1 data, wait for generation of write termination interrupt request while processing other than write is performed. When write termination interrupt request is generated, start next write operation. (2) Method using write status flag (EWST) Poll EWST (EEPROM write control register (EEWC) bit 1), and wait for EWST to become 0. When EWST becomes 0, start the next write operation. 4.6 EEPROM Control-Related Interrupt EEPROM write termination interrupt request (INTWE) is generated from EEPROM. INTWE is an interrupt request generated upon termination of EEPROM writing. This interrupt request is generated when the time set with EWCS0 and EWCS1 (EEPROM write control register (EEWC) bits 4 and 5) has elapsed. When this interrupt request is generated, data writing to EEPROM is terminated, indicating that writing of the next data is enabled. 71 CHAPTER 4 EEPROM 4.7 Cautions regarding EEPROM Writing The following shows cautions of EEPROM write. Before performing EEPROM write, be sure to read the following cautions. (1) Before writing, be sure to check that EWST (EEPROM write control register (EEWC) bit 1) is 0. If executing another write instructions during EEPROM writing, the instruction executed last will be ignored. (2) For write time, see Figure 4-2. (3) If performing several write operations in succession, be sure to wait until the current write operation is completed before starting the next one. (4) Even if the mode changes to HALT mode during EEPROM writing, writing is continued. (5) If the mode changes to STOP mode during EEPROM writing, the data being written becomes undefined. If this www..com STOP mode is cancelled by interrupt request, a write termination interrupt request (INTWE) is generated after the STOP mode has been cancelled. If you want to set the STOP mode after normally terminating write processing, check that write processing has ended using any of the available methods (refer to 4.5 EEPROM Writing), then set the STOP mode. (6) If you want to read the EEPROM contents immediately after changing EWCC (EEPROM write control register (EEWC) bit 2) from 1 to 0, set a wait time of 20 s or more by software. If no wait time is set, the data read will not be correct. 72 CHAPTER 5 PORT FUNCTIONS 5.1 Port Functions The PD780973 Subseries are provided with five input port pins, sixteen output port pins, and thirty-five input/output port pins. Figure 5-1 shows the port configuration. Every port can be manipulated in 1-bit or 8-bit units controlled in various ways. Moreover, the port pins can also serve as I/O pins of the internal hardware. Figure 5-1. Port Types www..com Port 4 Port 5 Port 6 Port 8 Port 9 P40 P00 P44 P50 P07 P10 P54 P60 P61 P81 Port 0 Port 1 Port 2 Port 3 P14 P20 P87 P27 P90 P30 P97 P37 73 CHAPTER 5 PORT FUNCTIONS Table 5-1. Port Functions Alternate Function INTP0 to INTP2 -- Pin Name P00 to P02 P03 to P07 Input/Output Input/Output Function Port 0 8-bit input/output port. Input/output mode can be specified bit-wise. If used as an input port, an on-chip pull-up resistor can be used by software. Port 1 5-bit input only port. Port 2 8-bit output only port. P10 to P14 Input ANI0 to ANI4 P20 to P23 P24 to www..com P27 P30 to P33 P34 to P37 P40 to P42 P43, P44 Output SM11 to SM14 SM21 to SM24 SM31 to SM34 SM41 to SM44 TI00 to TI02 TIO2, TIO3 Output Port 3 8-bit output only port. Input/Output Port 4 5-bit input/output port. Input/output mode can be specified bit-wise. Port 5 5-bit input/output port. Input/output mode can be specified bit-wise. P50 P51 P52 P53 P54 P60 P61 Input/Output SCK SO SI RxD TxD Input/Output Port 6 2-bit input/output port. Input/output mode can be specified bit-wise. Port 8 7-bit input/output port. Input/output mode can be specified bit-wise. Can be set in input/output port or segment output mode in 2-bit units by using LCD display control register (LCDC). Port 9 8-bit input/output port. Input/output mode can be specified bit-wise. Can be set in input/output port or segment output mode in 2-bit units by using LCD display control register (LCDC). PCL/SGOA SGO/SGOF P81 P82 to P87 Input/Output S19/TPO S18 to S13 P90 to P97 Input/Output S12 to S5 74 CHAPTER 5 PORT FUNCTIONS 5.2 Port Configuration A port consists of the following hardware: Table 5-2. Port Configuration Item Control register Configuration Port mode register (PMm: m = 0, 2 to 6, 8, 9) Pull-up resistor option register (PU0) Total: 56 lines (5 inputs, 16 outputs, 35 inputs/outputs) Total: 8 (software specifiable: 8) Port Pull-up resistor www..com 5.2.1 Port 0 Port 0 is an 8-bit input/output port with output latch. P00 to P07 pins can specify the input mode/output mode in 1-bit units with the port mode register 0 (PM0). When P00 to P07 pins are used as input ports, an on-chip pull-up resistor can be used to them in 1-bit units with a pull-up resistor option register (PU0). Alternate functions include external interrupt request input. RESET input sets port 0 to input mode. Figure 5-2 shows a block diagram of port 0. Caution Because port 0 also serves for external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. Thus, when the output mode is used, set the interrupt mask flag to 1. 75 CHAPTER 5 PORT FUNCTIONS Figure 5-2. P00 to P07 Block Diagram VDD WRPUO PU00 to PU07 P-ch RD Selector Internal bus WRPORT Output latch (P00 to P07) P00/INTP0 P02/INTP2 P03 to P07 www..com WRPM PM00 to PM07 PU : Pull-up resistor option register PM : Port mode register RD : Port 0 read signal WR : Port 0 write signal 5.2.2 Port 1 Port 1 is a 5-bit input only port. Alternate functions include an A/D converter analog input. Figure 5-3 shows a block diagram of port 1. Figure 5-3. P10 to P14 Block Diagram RD Internal bus P10/ANI0 P14/ANI4 RD : Port 1 read signal 76 CHAPTER 5 PORT FUNCTIONS 5.2.3 Port 2 Port 2 is an 8-bit output only port with output latch. P20 to P27 pins go into a high-impedance state when the ENn of port mode control register (PMC) is set to 0 and the port mode register 2 (PM2) is set to 1. Alternate functions include meter control PWM output. RESET input sets port 2 to high-impedance state. Figure 5-4 shows a block diagram of port 2. Figure 5-4. P20 to P27 Block Diagram RD www..com Internal bus WRPORT Output latch (P20 to P27) Selector P20/SM11 to P23/SM14 P24/SM21 to P27/SM24 WRPM PM20 to PM27 Alternate functions Decoder 2 MODn ENn DIRn1 DIRn0 PM : Port mode register RD : Port 2 read signal WR : Port 2 write signal Caution Remark When PM2 is set to 0, read operation is enabled. When PM2 is set to 1, read operation is disabled. n = 1, 2 77 CHAPTER 5 PORT FUNCTIONS 5.2.4 Port 3 Port 3 is an 8-bit output only port with output latch. P30 to P37 pins go into a high-impedance state when the ENn of port mode control register (PMC) is set to 0 and the port mode register 3 (PM3) is set to 1. Alternate functions include meter control PWM output. RESET input sets port 3 to high-impedance state. Figure 5-5 shows a block diagram of port 3. Figure 5-5. P30 to P37 Block Diagram RD www..com Internal bus WRPORT Output latch (P30 to P37) Selector P30/SM31 to P33/SM34 P34/SM41 to P37/SM44 WRPM PM30 to PM37 Alternate functions Decoder 2 MODn ENn DIRn1 DIRn0 PM : Port mode register RD : Port 3 read signal WR : Port 3 write signal Caution Remark When PM3 is set to 0, read operation is enabled. When PM3 is set to 1, read operation is disabled. n = 3, 4 78 CHAPTER 5 PORT FUNCTIONS 5.2.5 Port 4 Port 4 is a 5-bit input/output port with output latch. P40 to P44 pins can specify the input mode/output mode in 1-bit units with the port mode register 4 (PM4). Alternate functions also include timer input/output. RESET input sets port 4 to input mode. Figure 5-6 shows a block diagram of port 4. Figure 5-6. P40 to P44 Block Diagram RD www..com WRPORT Output latch (P40 to P44) Selector Internal bus P40/TI00 to P42/TI02 P43/TIO2 P44/TIO3 WRPM PM40 to PM44 Alternate functions PM RD : Port mode register : Port 4 read signal WR : Port 4 write signal 79 CHAPTER 5 PORT FUNCTIONS 5.2.6 Port 5 Port 5 is a 5-bit input/output port with output latch. P50 to P54 pins can specify the input mode/output mode in 1-bit units with the port mode register 5 (PM5). Alternate functions include serial interface data input/output and clock input/output. RESET input sets port 5 to input mode. Figure 5-7 shows a block diagram of port 5. Figure 5-7. P50 to P54 Block Diagram RD www..com WRPORT Output latch (P50 to P54) Selector Internal bus P50/SCK P51/SO P52/SI P53/RxD P54/TxD WRPM PM50 to PM54 Alternate functions PM : Port mode register RD : Port 5 read signal WR : Port 5 write signal 80 CHAPTER 5 PORT FUNCTIONS 5.2.7 Port 6 Port 6 is a 2-bit input/output port with output latch. P60 and P61 pins can specify the input mode/output mode in 1-bit units with the port mode register 6 (PM6). Alternate functions include clock output and sound generator output. RESET input sets port 6 to input mode. Figure 5-8 shows a block diagram of port 6. Figure 5-8. P60 and P61 Block Diagram RD www..com WRPORT Output latch (P60, P61) Selector Internal bus P60/PCL/SGOA P61/SGO/SGOF WRPM PM60, PM61 Alternate functions PM : Port mode register RD : Port 6 read signal WR : Port 6 write signal 81 CHAPTER 5 PORT FUNCTIONS 5.2.8 Port 8 Port 8 is a 7-bit input/output port with output latch. P81 to P87 pins can specify the input mode/output mode in 1-bit units with the port mode register 8 (PM8). Alternate functions also include segment signal output of the LCD controller/driver and prescaler signal output. Segment output and input/output port can be switched by setting the LCD display control register (LCDC). RESET input sets port 8 to input mode. Figures 5-9 and 5-10 show block diagrams of port 8. Figure 5-9. P81 Block Diagram RD www..com Selector WRPORT Output latch (P81) Internal bus P81/S19/TPO WRPM PM81 Alternate functions Segment output function Figure 5-10. P82 to P87 Block Diagram RD Selector WRPORT Output latch (P82 to P87) P82/S18 to P87/S13 Internal bus WRPM PM82 to PM87 Segment output function PM : Port mode register RD : Port 8 read signal WR : Port 8 write signal 82 CHAPTER 5 PORT FUNCTIONS 5.2.9 Port 9 Port 9 is an 8-bit input/output port with output latch. P90 to P97 pins can specify the input mode/output mode in 1-bit units with the port mode register 9 (PM9). Alternate functions also include segment signal output of the LCD controller/driver. Segment output and input/output port can be switched by setting the LCD display control register (LCDC). RESET input sets port 9 to input mode. Figure 5-11 shows a block diagram of port 9. Figure 5-11. P90 to P97 Block Diagram RD www..com Selector WRPORT Output latch (P90 to P97) P90/S12 to P97/S5 Internal bus WRPM PM90 to PM97 Segment output function PM : Port mode register RD : Port 9 read signal WR : Port 9 write signal 83 CHAPTER 5 PORT FUNCTIONS 5.3 Port Function Control Registers The following two types of registers control the ports. * Port mode registers (PM0, PM2 to PM6, PM8, PM9) * Pull-up resistor option register (PU0) (1) Port mode registers (PM0, PM2 to PM6, PM8, PM9) These registers are used to set port input/output in 1-bit units. PM0, PM2 to PM6, PM8, and PM9 are independently set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets registers to FFH. Cautions 1. Pins P10 and P14 are input-only pins, and pins P20 to P27 and P30 to P37 are outputwww..com only pins. 2. Port 0 has an alternate function as external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. When the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand. 3. Ports 2 and 3 that can be also used as meter driving PWM signal output pins go into a high-impedance state when 1 is set to PM2x and PM3x, respectively. 84 CHAPTER 5 PORT FUNCTIONS Table 5-3. Port Mode Register and Output Latch Settings when Using Alternate Functions Alternate Functions Name P00 P01 P02 P10 to P14 Note 1 P20 to P27 P30 to P37 P40 to P42 www..com P43, P44 P60 P61 P81, P82 to P87 P90 to P97 INTP0 INTP1 INTP2 ANI0 to ANI4 SM11 to SM24 SM31 to SM44 TI00 to TI02 TIO2, TIO3 SGOA/PCL SGO/SGOF Input/Output Pin Name PMxx Pxx Input Input Input Input Output Output Input Output Output Output 1 1 1 1 0 Note 2 0 Note 2 1 0 0 0 x Note 3 x Note 3 x x x x x x x 0 0 0 S19/TPO, S18 to S13 Output S12 to S5 Output Notes 1. If these ports are read out when these pins are used in the alternate function mode, undefined values are read. 2. The P20 to P27 and P30 to P37 pins have an alternate function as meter driving PWM signal output. When 0 is set to ENn (n = 1 to 4) of port mode control register (PMC) and 1 is set to PMxx, these pins go into the high-impedance state. Refer to the port mode register format. 3. When the P81 to P87 and P90 to P97 pins are used for alternate functions, set the function with the LCD display control register (LCDC). Caution When port 5 is used for serial interface, the I/O latch or output latch must be set according to their function. For the setting methods, see Figure 14-2 Asynchronous Serial Interface Mode Register (ASIM) Format and Figure 15-2 Serial Operation Mode Register (CSIM) Format. Remark x Pxx : don't care : port output latch PMxx : port mode register 85 CHAPTER 5 PORT FUNCTIONS Figure 5-12. Port Mode Register (PM0, PM4 to PM6, PM8, PM9) Format Address: FF20H After Reset : FFH Symbol PM0 7 PM07 6 PM06 R/W 5 PM05 4 PM04 3 PM03 2 PM02 1 PM01 0 PM00 Address: FF24H After Reset : FFH Symbol PM4 7 1 6 1 R/W 5 1 4 PM44 3 PM43 2 PM42 1 PM41 0 PM40 Address: FF25H After Reset : FFH www..com Symbol PM5 7 1 6 1 R/W 5 1 4 PM54 3 PM53 2 PM52 1 PM51 0 PM50 Address: FF26H After Reset : FFH Symbol PM6 7 1 6 1 R/W 5 1 4 1 3 1 2 1 1 PM61 0 PM60 Address: FF28H After Reset : FFH Symbol PM8 7 PM87 6 PM86 R/W 5 PM85 4 PM84 3 PM83 2 PM82 1 PM81 0 1 Address: FF29H After Reset : FFH Symbol PM9 7 PM97 6 PM96 R/W 5 PM95 4 PM94 3 PM93 2 PM92 1 PM91 0 PM90 PMmn 0 1 Pmn Pin Input/Output Mode Select (m = 0, 4 to 6, 8, 9 ; n = 0 to 7) Output Mode (Output buffer on) Input Mode (Output buffer off) Figure 5-13. Port Mode Register (PM2, PM3) Format Address: FF22H After Reset : FFH Symbol PM2 7 PM27 6 PM26 R/W 5 PM25 4 PM24 3 PM23 2 PM22 1 PM21 0 PM20 Address: FF23H After Reset : FFH Symbol PM3 7 PM37 6 PM36 R/W 5 PM35 4 PM34 3 PM33 2 PM32 1 PM31 0 PM30 PMmn 0 1 Pmn Pin Input/Output Mode Select (m = 2, 3 ; n = 0 to 7) Output Mode (Output buffer on) High-impedance state (Output buffer off) Note Note When 0 is set to ENn of port mode control register (PMC) 86 CHAPTER 5 PORT FUNCTIONS (2) Pull-up resistor option register (PU0) This register is used to set whether to use an internal pull-up resistor at port 0 or not. A pull-up resistor is internally used at bits which are set to the input mode at a port where pull-up resistor use has been specified with PU0. No pull-up resistors can be used to the bits set to the output mode irrespective of PU0 setting. PU0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 5-14. Pull-Up Resistor Option Register (PU0) Format Address: FF30H After Reset : 00H Symbol PU0 www..com PU0m 0 1 P0m Pin Internal Pull-Up Resistor Select (m = 0 to 7) On-chip pull-up resistor not used On-chip pull-up resistor used 7 PU07 6 PU06 R/W 5 PU05 4 PU04 3 PU03 2 PU02 1 PU01 0 PU00 87 CHAPTER 5 PORT FUNCTIONS 5.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 5.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. (2) Input mode www..com A value is written to the output latch by a transfer instruction, but since the output buffer is OFF, the pin status does not change. Once data is written to the output latch, it is retained until data is written to the output latch again. Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. 5.4.2 Reading from input/output port (1) Output mode The output latch contents are read by a transfer instruction. The output latch contents do not change. (2) Input mode The pin status is read by a transfer instruction. The output latch contents do not change. 5.4.3 Operations on input/output port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. (2) Input mode The output latch contents are undefined, but since the output buffer is OFF, the pin status does not change. Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. 88 CHAPTER 6 CLOCK GENERATOR 6.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. * Main system clock oscillator This circuit oscillates at frequencies of 4.19 to 8.38 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC). 6.2 Clock Generator Configuration www..com The clock generator consists of the following hardware. Table 6-1. Clock Generator Configuration Item Control register Configuration Processor clock control register (PCC) Oscillator mode register (OSCM) Note Main system clock oscillator Oscillator Note PD780973(A) only Figure 6-1. Clock Generator Block Diagram Prescaler X1 X2 Main system clock oscillator Prescaler fX fX 2 fX 22 fX 23 fX 24 Selector Standby control circuit CPU clock (fCPU) Clock to peripheral hardware STOP 3 HALFOSC Oscillator mode register PCC2 PCC1 PCC0 Processor clock control register Internal bus 89 CHAPTER 6 CLOCK GENERATOR 6.3 Clock Generator Control Register The following two types of registers are used to control the clock generator. * Processor clock control register (PCC) * Oscillator mode register (OSCM) (1) Processor clock control register (PCC) The PCC sets the division ratio of the CPU clock. The PCC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets the PCC to 04H. Figure 6-2. Processor Clock Control Register (PCC) Format www..com Address: FFFBH After Reset: 04H Symbol PCC 7 0 6 0 R/W 5 0 4 0 3 0 2 PCC2 1 PCC1 0 PCC0 PCC2 0 0 0 0 1 PCC1 0 0 1 1 0 PCC0 0 1 0 1 0 fX fX/2 fX/22 fX/23 fX/24 Setting prohibited CPU Clock (fCPU) Select Other than above Caution Bits 3 to 7 must be set to 0. : Main system clock oscillation frequency Remark fX The fastest instructions of the PD780973 Subseries are executed in two CPU clocks. Therefore, the relation between the CPU clock (fCPU) and the minimum instruction execution time is as shown in Table 6-2. Table 6-2. Relation between CPU Clock and Minimum Instruction Execution Time Minimum Instruction Execution Time: 2/fCPU fX = 8 MHz fX fX/2 fX/22 fX/23 fX/24 0.25 s 0.5 s 1.0 s 2.0 s 4.0 s fX = 8.38 MHz 0.24 s 0.48 s 0.95 s 1.91 s 3.81 s CPU Clock (fCPU) Remark fX : Main system clock oscillation frequency 90 CHAPTER 6 CLOCK GENERATOR (2) Oscillator mode register (OSCM) The PD780973(A) can be set to the reduced current consumption mode by setting OSCM (only when operated at fX = 4 to 4.19 MHz). OSCM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets OSCM to 00H. Figure 6-3. Oscillator Mode Register (OSCM) Format Address: FFA0H After Reset: 00H Symbol OSCM www..com 7 HALFOSC 6 0 R/W 5 0 4 0 3 0 2 0 1 0 0 0 HALFOSC 0 1 Normal operation mode Oscillator Mode Selection Reduced current consumption mode (only when operated at fX = 4 to 4.19 MHz) Cautions 1. This function is available only when the device is operated at fX = 4 to 4.19 MHz. In other cases, be sure not to set 1 to bit 7. 2. When using in normal operation mode, setting OSCM is not necessary. 3. Only the first setting of OSCM is effective. 91 CHAPTER 6 CLOCK GENERATOR 6.4 System Clock Oscillator 6.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 8.38 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin and an inverted clock signal to the X2 pin. Figure 6-4 shows an external circuit of the main system clock oscillator. Figure 6-4. External Circuit of Main System Clock Oscillator (a) Crystal and ceramic oscillation www..com IC X2 X2 (b) External clock X1 Crystal resonator or ceramic resonator External clock X1 PD74HCU04 Caution Do not execute the STOP instruction while an external clock is input. This is because if the STOP instruction is executed, the main system clock operation is stopped, and the X2 pin is connected to VDD, via a pull-up resistor. 92 CHAPTER 6 CLOCK GENERATOR Caution When using a main system clock oscillator, carry out wiring in the broken line area in Figure 6-4 as follows to avoid influence of wiring capacity. * Keep the wiring length as short as possible. * Do not cross the wiring with any other signal lines. Do not route the wiring in the vicinity of a line through which a high alternating current flows. * Always keep the ground of the capacitor of the oscillator at the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Figure 6-5 shows examples of resonator having bad connection. Figure 6-5. Incorrect Examples of Resonator Connection (1/2) www..com (a) Too long wiring (b) Crossed signal line PORTn (n = 0 to 6, 8 and 9) IC X2 X1 IC X2 X1 93 CHAPTER 6 CLOCK GENERATOR Figure 6-5. Incorrect Examples of Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) VDD Pmn IC www..com X2 X1 IC X2 X1 High current A B High current C (e) Signals are fetched IC X2 X1 6.4.2 Divider circuit The divider circuit divides the output of the main system clock oscillation circuit (fX) to generate various clocks. 94 CHAPTER 6 CLOCK GENERATOR 6.5 Operation of Clock Generator The clock generator generates the following clocks and controls the operation modes of the CPU, such as the standby mode: * Main system clock * CPU clock fCPU fX * Clock to peripheral hardware The operation of the clock generator is determined by the processor clock control register (PCC) and oscillator mode register (OSCM) as follows: www..com (a) The slowest mode (3.81 s: at 8.38-MHz operation) of the main system clock is selected when the RESET signal is generated (PCC = 04H). While a low level is input to the RESET pin, oscillation of the main system clock is stopped. (b) Five types of CPU clocks (0.24 s, 0.48 s, 0.95 s, 1.91 s, and 3.81 s: at 8.38-MHz operation) can be selected by the PCC setting. (c) Two standby modes, STOP and HALT, can be used. (d) The clock to the peripheral hardware is supplied by dividing the main system clock. The other peripheral hardware is stopped when the main system clock is stopped (except, however, the external clock input operation). (e) The PD780973(A) can be set to the reduced current consumption mode by setting OSCM (only when operated at fX = 4 to 4.19 MHz). Setting 1 to bit 7 (HALFOSC) of OSCM will reduce the power consumption. Cautions 1. This function is available only when the device is operated at fX = 4 to 4.19 MHz. In other cases, be sure not to set 1 to bit 7. 2. When using in normal operation mode, setting OSCM is not necessary. 3. Only the first setting of OSCM is effective. 95 CHAPTER 6 CLOCK GENERATOR 6.6 Changing Setting of CPU Clock 6.6.1 Time required for switching CPU clock The CPU clock can be selected by using bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC). Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old clock is used for the duration of several instructions after that (refer to Table 6-3). Table 6-3. Maximum Time Required for Switching CPU Clock Set Value before Switching PCC2 PCC1 PCC0 0 www..com 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 8 instructions 4 instructions 2 instructions 1 instruction 4 instructions 2 instructions 1 instruction 2 instructions 1 instruction 1 instruction 0 0 0 0 1 0 1 0 0 1 1 1 0 0 16 instructions 16 instructions 8 instructions 16 instructions 8 instructions 4 instructions 16 instructions 8 instructions 4 instructions 2 instructions Set Value after Switching PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 Remark One instruction is the minimum instruction execution time of the CPU clock before switching. 96 CHAPTER 6 CLOCK GENERATOR 6.6.2 Switching CPU clock The following figure illustrates how the CPU clock switches. Figure 6-6. Switching CPU Clock VDD RESET www..com CPU clock Slowest operation Fastest operation Wait (15.6 ms: at 8.38-MHz operation) Internal reset operation <1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released when the RESET pin is later made high, and the main system clock starts oscillating. At this time, the time during which oscillation stabilizes (217/fX) is automatically secured. After that, the CPU starts instruction execution at the slowest speed of the main system clock (3.81 s: at 8.38-MHz operation). <2> After the time during which the VDD voltage rises to the level at which the CPU can operate at the highest speed has elapsed, PCC is rewritten so that the highest speed can be selected. 97 [MEMO] www..com 98 CHAPTER 7 16-BIT TIMER 0 TM0 7.1 Outline of Internal Timer of PD780973 Subseries This chapter explains the 16-bit timer 0. Before that, the internal timers of the PD780973 Subseries, and the related functions are briefly explained below. (1) 16-bit timer 0 TM0 The TM0 can be used for pulse widths measurement, divided output of input pulse. (2) 8-bit timer 1 TM1 www..com The TM1 can be used for an interval timer (See CHAPTER 8 8-BIT TIMER 1 TM1). (3) 8-bit timer/event counters 2, 3 TM2, TM3 TM2 and TM3 can be used to serve as an interval timer and an external event counter and to output square waves with any selected frequency, PWM output (See CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3). (4) Watch timer This timer can set a flag every 0.5 sec. and simultaneously generates interrupt request at the preset time intervals (See CHAPTER 10 WATCH TIMER). (5) Watchdog timer This timer can perform the watchdog timer function or generate non-maskable interrupt request, maskable interrupt request and RESET at the preset time intervals (See CHAPTER 11 WATCHDOG TIMER). (6) Clock output control circuit Clock output supplies other devices with the divided main system clock (See CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT). 99 CHAPTER 7 16-BIT TIMER 0 TM0 Table 7-1. Timer/Event Counter Operations 8-bit Timer/Event Counter TM2, TM3 2 channels 16-bit Timer TM0 8-bit Timer TM1 Operating mode Function Interval timer External event counter Timer output PWM output Pulse width measurement Square-wave output Divided output www..com Interrupt request - - - - - 1 channel - - - - - - Watch Timer 1 channel Note 1 - - - Watchdog Timer 1 channel Note 2 - - - - - - - - - - - Notes 1. Watch timer can perform both watch timer and interval timer functions at the same time. 2. Watchdog timer can perform either the watchdog timer function or the interval timer function, as selected. 7.2 16-Bit Timer 0 Functions The 16-bit timer 0 (TM0) has the following functions. * Pulse width measurement * Divided output of input pulse Figure 7-1 shows 16-bit timer 0 block diagram. 100 CHAPTER 7 16-BIT TIMER 0 TM0 Figure 7-1. Timer 0 (TM0) Block Diagram Internal bus Capture pulse control register (CRC0) CRC01 CRC00 Prescaler mode register (PRM0) ES21 ES20 ES11 ES10 ES01 ES00 PRM01 PRM00 16-bit timer mode control register (TMC0) TMC02 TPOE fX/8 fX/16 fX/32 fX/64 Selector 16-bit timer register (TM0) INTOVF ES21, ES20 www..com TI02/P42 Noise rejection circuit Prescaler 1, 1/2, 1/4, 1/8 Edge detection circuit ES11, ES10 16-bit capture register (CR02) INTTM02 16-bit capture register (CR01) INTTM01 16-bit capture register (CR00) INTTM00 TI01/P41 Noise rejection circuit Edge detection circuit ES01, ES00 TI00/P40 Noise rejection circuit Edge detection circuit TPO/P81/S19 TPOE Internal bus (1) Pulse width measurement TM0 can measure the pulse width of an externally input signal. (2) Divided output of input pulse The frequency of an input signal can be divided and the divided signal can be output. 101 CHAPTER 7 16-BIT TIMER 0 TM0 7.3 16-Bit Timer 0 Configuration Timer 0 consists of the following hardware. Table 7-2. Timer 0 Configuration Item Timer register Register Control register 16 bits x 1 (TM0) Capture register: 16 bits x 3 (CR00 to CR02) 16-bit timer mode control register (TMC0) Capture pulse control register (CRC0) Prescaler mode register (PRM0) Configuration www..com (1) 16-bit timer register (TM0) TM0 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of an input clock. If the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read. The count value is reset to 0000H in the following cases: <1> At RESET input <2> If TMC02 is cleared (2) Capture register 00 (CR00) The valid edge of the TI00 pin can be selected as the capture trigger. Setting of the TI00 valid edge is performed by setting of the prescaler mode register (PRM0). When the valid edge of the TI00 is detected, an interrupt request (INTTM00) is generated. CR00 is read by a 16-bit memory manipulation instruction. After RESET input, the value of CR00 is undefined. (3) Capture register 01 (CR01) The valid edge of the TI01 pin can be selected as the capture trigger. Setting of the TI01 valid edge is performed by setting of the prescaler mode register (PRM0). When the valid edge of the TI01 is detected, an interrupt request (INTTM01) is generated. CR01 is read by a 16-bit memory manipulation instruction. After RESET input, the value of CR01 is undefined. (4) Capture register 02 (CR02) The valid edge of the TI02 pin can be selected as the capture trigger. Setting of the TI02 valid edge is performed by setting of the prescaler mode register (PRM0). When the valid edge of the TI02 is detected, an interrupt request (INTTM02) is generated. CR02 is read by a 16-bit memory manipulation instruction. After RESET input, the value of CR02 is undefined. 102 CHAPTER 7 16-BIT TIMER 0 TM0 7.4 16-Bit Timer 0 Control Registers The following three types of registers are used to control timer 0. * 16-bit timer mode control register (TMC0) * Capture pulse control register (CRC0) * Prescaler mode register (PRM0) (1) 16-bit timer mode control register (TMC0) This register sets the 16-bit timer operating mode and controls the prescaler output signals. TMC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears TMC0 value to 00H. www..com Figure 7-2. 16-Bit Timer Mode Control Register (TMC0) Format Address: FF72H Symbol TMC0 7 0 After Reset: 00H 6 0 R/W 5 0 4 0 3 0 2 TMC02 1 0 0 TPOE TMC02 0 1 Timer 0 Operating Mode Selection Operation stop (TM0 cleared to 0) Operation enabled TPOE 0 1 Timer 0 Prescaler Output Control Prescaler signal output disabled Prescaler signal output enabled Cautions 1. Before changing the operation mode, stop the timer operation (by setting 0 to TMC02). 2. Bit 1 and bits 3 to 7 must be set to 0. 103 CHAPTER 7 16-BIT TIMER 0 TM0 (2) Capture pulse control register (CRC0) This register specifies the division ratio of the capture pulse input to the 16-bit capture register (CR02) from an external source. CRC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CRC0 value to 04H. Figure 7-3. Capture Pulse Control Register (CRC0) Format Address: FF71H Symbol CRC0 www..com 7 0 After Reset: 00H 6 0 R/W 5 0 4 0 3 0 2 0 1 CRC01 0 CRC00 CRC01 0 0 1 1 CRC00 0 1 0 1 Capture Pulse Selection Does not divide capture pulse Divides capture pulse by 2 Divides capture pulse by 4 Divides capture pulse by 8 Cautions 1. Timer operation must be stopped before setting CRC0. 2. Bits 2 to 7 must be set to 0. 104 CHAPTER 7 16-BIT TIMER 0 TM0 (3) Prescaler mode register (PRM0) This register is used to set 16-bit timer (TM0) count clock and valid edge of TI0n (n = 0 to 2) input. PRM0 is set with an 8-bit memory manipulation instruction. RESET input sets PRM0 value to 00H. Figure 7-4. Prescaler Mode Register (PRM0) Format Address: FF70H Symbol PRM0 7 ES21 After Reset: 00H 6 ES20 R/W 5 ES11 4 ES10 3 ES01 2 ES00 1 PRM01 0 PRM00 ES21 www..com 0 0 1 1 ES20 0 1 0 1 Falling edge Rising edge Setting prohibited TI02 Valid Edge Selection Both falling and rising edges ES11 0 0 1 1 ES10 0 1 0 1 Falling edge Rising edge Setting prohibited TI01 Valid Edge Selection Both falling and rising edges ES01 0 0 1 1 ES00 0 1 0 1 Falling edge Rising edge Setting prohibited TI00 Valid Edge Selection Both falling and rising edges PRM01 0 0 1 1 PRM00 0 1 0 1 fX/23 fX/24 fX/25 fX/26 Count Clock Selection Caution Timer operation must be stopped before setting PRM0. 105 CHAPTER 7 16-BIT TIMER 0 TM0 7.5 16-Bit Timer 0 Operations 7.5.1 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00/P40 to TI02/P42 pins using the 16-bit timer register (TM0). TM0 is used in free-running mode. (1) Pulse width measurement with free-running counter and one capture register (TI00) When the edge specified by prescaler mode register (PRM0) is input to the TI00/P40 pin, the value of TM0 is taken into 16-bit capture register 00 (CR00) and an external interrupt request signal (INTTM00) is set. Any of three edge specifications can be selected--rising, falling, or both edges--by means of bits 2 and 3 (ES00 and ES01) of PRM0. For valid edge detection, sampling is performed at the count clock selected by PRM0, and a capture operation www..comonly performed when a valid level is detected twice, thus eliminating noise with a short pulse width. is Figure 7-5. Configuration Diagram for Pulse Width Measurement by Free-Running Counter fX/23 fX/24 fX/25 fX/26 Selector 16-bit timer register (TM0) INTOVF TI00 16-bit capture register 00 (CR00) INTTM00 Internal bus Figure 7-6. Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) t Count clock TM0 count value TI00 pin input Value loaded to CR00 INTTM00 D0 D1 D2 D3 0000H 0001H D0 D1 FFFFH 0000H D2 D3 INTOVF (D1 - D0) x t (10000H - D1 + D2) x t (D3 - D2) x t 106 CHAPTER 7 16-BIT TIMER 0 TM0 (2) Measurement of three pulse widths with free-running counter The 16-bit timer register (TM0) allows simultaneous measurement of the pulse widths of the three signals input to the TI00/P40 to TI02/P42 pins. When the edge specified by bits 2 and 3 (ES00 and ES01) of prescaler mode register (PRM0) is input to the TI00/P40 pin, the value of TM0 is taken into 16-bit capture register 00 (CR00) and an external interrupt request signal (INTTM00) is set. Also, when the edge specified by bits 4 and 5 (ES10 and ES11) of PRM0 is input to the TI01/P41 pin, the value of TM0 is taken into 16-bit capture register 01 (CR01) and an external interrupt request signal (INTTM01) is set. When the edge specified by bits 6 and 7 (ES20 and ES21) of PRM0 is input to the TI02/P42 pin, the value of TM0 is taken into 16-bit capture register 02 (CR02) and external interrupt request signal (INTTM02) is set. Any of three edge specifications can be selected--rising, falling, or both edges--as the valid edges for the TI00/ P40 to TI02/P42 pins by means of bits 2 and 3 (ES00 and ES01), bits 4 and 5 (ES10 and ES11), and bits 6 and www..com 7 (ES06 and ES07) of PRM0, respectively. For TI00/P40 pin valid edge detection, sampling is performed at the interval selected by means of the prescaler mode register (PRM0), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. * Capture operation Capture register operation in capture trigger input is shown. Figure 7-7. CR0m Capture Operation with Rising Edge Specified Count clock TM0 TI0m Rising edge detection CR0m INTTM0m n n-3 n-2 n-1 n n+1 Remark m = 0 to 2 107 CHAPTER 7 16-BIT TIMER 0 TM0 Figure 7-8. Timing of Pulse Width Measurement Operation by Free-Running Counter (with Both Edges Specified) t Count clock TM0 count value TI0m pin input Value loaded to CR0m INTTM0m www..com 0000H 0001H D0 D1 FFFFH 0000H D2 D3 D0 D1 D2 D3 TI0n pin input Value loaded to CR0n INTTM0n INTOVF (D1 - D0) x t (10000H - D0 + D2) x t (10000H - D1 + (D2 + 1) x t (D3 - D2) x t D1 Remark m = 0 to 2, n = 1, 2 108 CHAPTER 7 16-BIT TIMER 0 TM0 7.6 16-Bit Timer 0 Cautions (1) Timer start errors An error with a maximum of one clock may occur until counting is started after timer start. This is because the 16-bit timer register (TM0) is started asynchronously with the count pulse. Figure 7-9. 16-Bit Timer Register Start Timing Count pulse TM0 count value www..com 0000H 0001H 0002H 0003H 0004H Timer start (2) Capture register data retention timings If the valid edge of the TI0m/P4m pin is input during 16-bit capture register 0m (CR0m) read, CR0m performs capture operation, but the capture value is not guaranteed. However, the interrupt request flag (INTTM0m) is set upon detection of the valid edge. Figure 7-10. Capture Register Data Retention Timing Count pulse TM0 count value Edge input Interrupt request flag Capture read signal CR0m interrupt value X N+1 N N+1 N+2 M M+1 M+2 Capture operation Remark m = 0 to 2 (3) Valid edge setting Set the valid edge of the TI0m/P4m pin after setting bit 2 (TMC02) of the 16-bit timer mode control register to 0, and then stopping timer operation. Valid edge setting is carried out with bits 2 to 7 (ESm0 and ESm1) of the prescaler mode register (PRM0). Remark m = 0 to 2 109 CHAPTER 7 16-BIT TIMER 0 TM0 (4) Occurrence of INTTM0n INTTM0n occurs even if no capture pulse exists, immediately after the timer operation has been started (TMC02 of TMC0 has been set to 1) with a high level applied to input pins TI00 to TI02 of 16-bit timer 0, and with the rising edge (with ESn1 and ESn0 of PRM0 set to 0, 1), or both the rising and falling edges (with ESn1 and ESn0 of PRM0 set to 1, 1) selected. However, INTTM0n does not occur if a low level is applied to TI00 to TI02. www..com 110 CHAPTER 8 8-BIT TIMER 1 TM1 8.1 8-Bit Timer 1 Functions The 8-bit timer 1 operates as an 8-bit interval timer. Figure 8-1 shows timer 1 block diagram. Figure 8-1. Timer 1 (TM1) Block Diagram Internal bus www..com 8-bit compare register 1 (CR1) Coincidence fX/23 fX/24 fX/25 fX/27 fX/29 fX/211 INTTM1 Selector 8-bit counter (TM1) Clear 3 TCL12 TCL11 TCL10 Timer clock select register 1 (TCL1) Internal bus TCE1 Timer mode control register (TMC1) 111 CHAPTER 8 8-BIT TIMER 1 TM1 8.2 8-Bit Timer 1 Configuration Timer 1 consists of the following hardware. Table 8-1. Timer 1 Configuration Item Timer register Register Control register 8-bit counter 1 (TM1) 8-bit compare register 1 (CR1) Timer clock select register 1 (TCL1) 8-bit timer mode control register 1 (TMC1) Configuration www..com Remark n = 0, 1 (1) 8-bit counter 1 (TM1) TM1 is an 8-bit read-only register which counts the count pulses. The counter is incremented in synchronization with the rising edge of the count clock. When count value is read during operation, count clock input is temporary stopped, and then the count value is read. In the following situations, the count value is set to 00H. <1> RESET input <2> Clear TCE1 <3> Match between TM1 and CR1 (2) 8-bit compare register 1 (CR1) The value set in the CR1 is constantly compared with the 8-bit counter 1 (TM1) count value, and an interrupt request (INTTM1) is generated if they match. It is possible to rewrite the value of CR1 within 00H to FFH during count operation. 112 CHAPTER 8 8-BIT TIMER 1 TM1 8.3 8-Bit Timer 1 Control Registers The following two types of registers are used to control timer 1. * Timer clock select register 1 (TCL1) * 8-bit timer mode control register 1 (TMC1) (1) Timer clock select register 1 (TCL1) This register sets count clocks of timer 1. TCL1 is set with an 8-bit memory manipulation instruction. RESET input clears to 00H. www..com Figure 8-2. Timer Clock Select Register 1 (TCL1) Format Address: FF73H Symbol TCL1 7 0 After Reset: 00H 6 0 R/W 5 0 4 0 3 0 2 TCL12 1 TCL11 0 TCL10 TCL12 0 0 0 0 1 1 1 1 TCL11 0 0 1 1 0 0 1 1 TCL10 0 1 0 1 0 1 0 1 Setting prohibited Setting prohibited fX/23 (1.04 MHz) fX/24 (523 kHz) fX/25 (261 kHz) fX/27 (65.4 kHz) fX/29 (16.3 kHz) fX/211 (4.09 kHz) Count Clock Selection Cautions 1. When rewriting TCL1 to other data, stop the timer operation beforehand. 2. Set bits 3 to 7 to 0. Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 8.38 MHz 113 CHAPTER 8 8-BIT TIMER 1 TM1 (2) 8-bit timer mode control register 1 (TMC1) TMC1 is a register that controls the counting operation of the 8-bit counter 1 (TM1). TMC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets to 04H. Figure 8-3 shows TMC1 format. Figure 8-3. 8-Bit Timer Mode Control Register 1 (TMC1) Format Address: FF76H Symbol TMC1 www..com 7 TCE1 After Reset: 04H 6 0 R/W 5 0 4 0 3 0 2 1 1 0 0 0 TCE1 0 1 Timer 1 Count Operation Control After clearing counter to 0, count operation disabled Count operation start Caution Be sure to set 0 to bit 0, bit 1, and bits 3 to 6, and set 1 to bit 2. 114 CHAPTER 8 8-BIT TIMER 1 TM1 8.4 8-Bit Timer 1 Operations 8.4.1 8-bit interval timer operation The 8-bit timer 1 operates as an interval timer which generates interrupt requests repeatedly at intervals of the count value preset to 8-bit compare register 1 (CR1). When the count values of the 8-bit counter 1 (TM1) match the values set to CR1, counting continues with the TM1 values cleared to 0 and the interrupt request signal (INTTM1) is generated. Count clock of the TM1 can be selected with bits 0 to 2 (TCL10 to TCL12) of the timer clock select register 1 (TCL1). [Setting] <1> Set the registers. * TCL1 : Select count clock. www..com * CR1 : Compare value <2> After TCE1 = 1 is set, count operation starts. <3> If the values of TM1 and CR1 match, the INTTM1 is generated and TM1 is cleared to 00H. <4> INTTM1 generates repeatedly at the same interval. Set TCE1 to 0 to stop count operation. Figure 8-4. Interval Timer Operation Timings (1/3) (a) Basic operation t Count clock TM1 count value 00H 01H N 00H 01H N 00H 01H N Start count CR1 TCE1 INTTM1 N Clear N Clear N N Interrupt received TM1 interval time Note Interval time Interval time Interrupt received Interval time Remark Interval time = (N + 1) x t: N = 00H to FFH 115 CHAPTER 8 8-BIT TIMER 1 TM1 Figure 8-4. Interval Timer Operation Timings (2/3) (b) When CR1 = 00H t Count clock TM1 00H CR1 TCE1 00H 00H 00H 00H www..com INTTM1 TM1 interval time Interval time (c) When CR1 = FFH t Count clock TM1 CR1 TCE1 INTTM1 Interrupt received TM1 interval time Interval time Interrupt received FF 01 FE FF FF 00 FE FF FF 00 116 CHAPTER 8 8-BIT TIMER 1 TM1 Figure 8-4. Interval Timer Operation Timings (3/3) (d) Operated by CR1 transition (M < N) Count clock TM1 N 00H CR1 TCE1 INTTM1 N M N FFH 00H M M 00H www..com TM1 interval time CR1 transition TM1 overflows since M < N (e) Operated by CR1 transition (M > N) Count clock TM1 CR1 TCE1 INTTM1 TM1 interval time CR1 transition N-1 N N 00H 01H N M M-1 M 00H 01H 117 CHAPTER 8 8-BIT TIMER 1 TM1 8.5 8-Bit Timer 1 Cautions (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. This is because 8-bit counter 1 (TM1) is started asynchronously with the count pulse. Figure 8-5. Timer 1 Start Timing Count pulse TM1 count value 00H Timer start 01H 02H 03H 04H www..com (2) Operation after compare register change during timer count operation If the values after the 8-bit compare register 1 (CR1) is changed are smaller than the value of 8-bit timer register 1 (TM1), TM1 continues counting, overflows and then restarts counting from 0. Thus, if the value (M) after CR1 change is smaller than value (N) before the change, it is necessary to restart the timer after changing CR1. Figure 8-6. Timing after Compare Register Change during Timer Count Operation Count pulse CR1 TM1 count value N X-1 X FFH M 00H 01H 02H Remark N > X > M Caution Always set TCE1 = 0 before setting the STOP state. (3) TM1 reading during timer operation When TM1 is read during operation, choose a count clock which has a longer high/low level wave because 8bit counter (TM1) is stopped temporary. 118 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 9.1 8-Bit Timer/Event Counters 2 and 3 Functions The 8-bit timer/event counters 2 and 3 operate as an 8-bit timer/event counter. TM2 and TM3 can have the following functions. * Interval timer * External event counter * Square wave output * PWM output www..com Figure 9-1 shows timer 2 block diagram, and Figure 9-2 shows timer 3 block diagram. Figure 9-1. Timer 2 (TM2) Block Diagram Internal bus Mask circuit 8-bit compare register 2 (CR2) TIO2/P43 fX/23 fX/25 fX/27 fX/28 fX/29 fX/211 Coincidence Selector INTTM2 Selector 8-bit counter 2 OVF (TM2) Clear Selector S Q INV R TIO2/P43 P43 output latch PM43 Note 3 Selector S R Invert level TCL22 TCL21 TCL20 Timer clock select register 2 (TCL2) TCE2 TMC26 LVS2 LVR2 TMC21 TOE2 Timer mode control register 2 (TMC2) Internal bus Note Bit 3 of port mode register (PM4) 119 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 Figure 9-2. Timer 3 (TM3) Block Diagram Internal bus Mask circuit 8-bit compare register 3 (CR3) TIO3/P44 fX/24 fX/26 fX/27 fX/28 fX/210 fX/212 Coincidence Selector Selector INTTM3 8-bit counter 3 OVF (TM3) Clear Selector S Q INV R TIO3/P44 P44 output latch PM44 Note www..com 3 Selector S R Invert level TCL32 TCL31 TCL30 Timer clock select register 3 (TCL3) TCE3 TMC36 LVS3 LVR3 TMC31 TOE3 Timer mode control register 3 (TMC3) Internal bus Note Bit 4 of port mode register 4 (PM4) 120 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 9.2 8-Bit Timer/Event Counters 2 and 3 Configurations Timers 2 and 3 consist of the following hardware. Table 9-1. Timers 2 and 3 Configurations Item Timer register Register Timer output Control register www..com 8-bit counter n (TMn) 8-bit compare register n (CRn) 2 (TIOn) Timer clock select register n (TCLn) 8-bit timer mode control register n (TMCn) Configuration Remark n = 2, 3 (1) 8-bit counter n (TMn: n = 2, 3) TMn is an 8-bit read-only register which counts the count pulses. The counter is incremented in synchronization with the rising edge of the count clock. When count value is read during operation, count clock input is temporary stopped, and then the count value is read. In the following situations, the count value is set to 00H. <1> RESET input <2> Clear TCEn <3> Match between TMn and CRn in clear and start made with match between TMn and CRn Remark n = 2, 3 (2) 8-bit compare register n (CRn: n = 2, 3) The value set in the CRn is constantly compared with the 8-bit counter n (TMn) count value, and an interrupt request (INTTMn) is generated if they match (except PWM mode). It is possible to rewrite the value of CRn within 00H to FFH during count operation. Remark n = 2, 3 121 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 9.3 8-Bit Timer/Event Counters 2 and 3 Control Registers The following two types of registers are used to control timers 2 and 3. * Timer clock select register n (TCLn) * 8-bit timer mode control register n (TMCn) n = 2, 3 (1) Timer clock select register n (TCLn: n = 2, 3) This register sets count clocks of timers 2 and 3. TCLn is set with an 8-bit memory manipulation instruction. www..com RESET input sets to 00H. Figure 9-3. Timer Clock Select Register 2 (TCL2) Format Address: FF74H Symbol TCL2 7 0 After Reset: 00H 6 0 R/W 5 0 4 0 3 0 2 TCL22 1 TCL21 0 TCL20 TCL22 0 0 0 0 1 1 1 1 TCL21 0 0 1 1 0 0 1 1 TCL20 0 1 0 1 0 1 0 1 TIO2 Falling edge TIO2 Rising edge fX/23 (1.04 MHz) fX/25 (261 kHz) fX/27 (65.4 kHz) fX/28 (32.7 kHz) fX/29 (16.3 kHz) fX/211 (4.09 kHz) Count Clock Selection Cautions 1. When rewriting TCL2 to other data, stop the timer operation beforehand. 2. Set bits 3 to 7 to 0. Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 8.38 MHz 122 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 Figure 9-4. Timer Clock Select Register 3 (TCL3) Format Address: FF75H Symbol TCL3 7 0 After Reset: 00H 6 0 R/W 5 0 4 0 3 0 2 TCL32 1 TCL31 0 TCL30 TCL32 0 0 0 0 www..com 1 1 1 1 TCL31 0 0 1 1 0 0 1 1 TCL30 0 1 0 1 0 1 0 1 TIO3 Falling edge TIO3 Rising edge fX/24 (523 kHz) fX/26 (130 kHz) fX/27 (65.4 kHz) fX/28 (32.7 kHz) fX/210 (8.18 kHz) fX/212 (2.04 kHz) Count Clock Selection Cautions 1. When rewriting TCL3 to other data, stop the timer operation beforehand. 2. Set bits 3 to 7 to 0. Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 8.38 MHz (2) 8-bit timer mode control register n (TMCn: n = 2, 3) TMCn is a register which sets up the following five types. <1> 8-bit counter n (TMn) count operation control <2> 8-bit counter n (TMn) operating mode selection <3> Timer output F/F (flip flop) status setting <4> Active level selection in timer F/F control or PWM (free-running) mode. <5> Timer output control TMCn is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets to 04H. Figure 9-5 shows TMCn format. 123 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 Figure 9-5. 8-Bit Timer Mode Control Register n (TMCn) Format Address: FF77H (TMC2) Symbol TMCn 7 TCEn FF78H (TMC3) 6 TMCn6 5 0 After Reset: 04H 4 0 R/W 3 LVSn 2 LVRn 1 TMCn1 0 TOEn TCEn 0 1 TM2, TM3 Count Operation Control After clearing counter to 0, count operation disabled (prescaler disabled) Count operation start TMCn6 www..com 0 1 TM2, TM3 Operating Mode Selection Clear and start mode by matching between TMn and CRn PWM (Free-running) mode LVSn 0 0 1 1 LVRn 0 1 0 1 No change Timer Output F/F Status Setting Timer output F/F reset (to 0) Timer output F/F set (to 1) Setting prohibited In Other Modes (TMCn6 = 0) TMCn1 0 1 Timer F/F Control Inversion operation disabled Inversion operation enabled In PWM Mode (TMCn6 = 1) Active Level Selection Active high Active low TOEn 0 1 Output disabled (Port mode) Output enabled Timer Output Control Cautions 1. Set bit 4 and bit 5 to 0. 2. Bit 2 and bit 3 are write-only. Remarks 1. In PWM mode, PWM output will be inactive because of TCEn = 0. 2. If LVSn and LVRn are read after data is set, they will be 0. 3. n = 2, 3 124 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 9.4 8-Bit Timer/Event Counters 2 and 3 Operations 9.4.1 8-bit interval timer operation The 8-bit timer/event counters operate as interval timers which generate interrupt requests repeatedly at intervals of the count value preset to 8-bit compare register n (CRn). When the count values of the 8-bit counter n (TMn) match the values set to CRn, counting continues with the TMn values cleared to 0 and the interrupt request signal (INTTMn) is generated. Count clock of the TMn can be selected with bits 0 to 2 (TCLn0 to TCLn2) of the timer clock select register n (TCLn). [Setting] <1> Set the registers. * TCLn : Select count clock. www..com * CRn : Compare value (TMCn = 0000xxx0B x = don't care) * TMCn : Select clear and start mode by match of TMn and CRn. <2> After TCEn = 1 is set, count operation starts. <3> If the values of TMn and CRn match, the INTTMn is generated and TMn is cleared to 00H. <4> INTTMn generates repeatedly at the same interval. Set TCEn to 0 to stop count operation. Remark n = 2, 3 Figure 9-6. Interval Timer Operation Timings (1/3) (a) Basic operation t Count clock TMn count value 00H 01H N 00H 01H N 00H 01H N Start count CRn TCEn INTTMn N Clear N Clear N N Interrupt received TIOn Interval time Interval time Interrupt received Interval time Remarks 1. Interval time = (N + 1) x t: N = 00H to FFH 2. n = 2, 3 125 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 Figure 9-6. Interval Timer Operation Timings (2/3) (b) When CRn = 00H t Count clock TMn 00H CRn TCEn 00H 00H 00H 00H www..com INTTMn TIOn Interval time (c) When CRn = FFH t Count clock TMn CRn TCEn INTTMn Interrupt received TIOn Interval time Interrupt received FF 01 FE FF FF 00 FE FF FF 00 n=2,3 126 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 Figure 9-6. Interval Timer Operation Timings (3/3) (d) Operated by CRn transition (M < N) Count clock TMn N 00H CRn TCEn INTTMn N M N FFH 00H M M 00H www..com TIOn CRn transition TMn overflows since M < N (e) Operated by CRn transition (M > N) Count clock TMn CRn TCEn INTTMn TIOn CRn transition N-1 N N 00H 01H N M M-1 M 00H 01H n = 2, 3 9.4.2 External event counter operation The external event counter counts the number of external clock pulses to be input to the TIOn. TMn is incremented each time the valid edge specified with the timer clock select register n (TCLn) is input. Either the rising or falling edge can be selected. When the TMn counted values match the values of 8-bit compare register n (CRn), TMn is cleared to 0 and the interrupt request signal (INTTMn) is generated. Whenever the TMn value matches the value of CRn, INTTMn is generated. Remark n = 2, 3 127 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 Figure 9-7. External Event Counter Operation Timings (with Rising Edge Specified) TIOn TMn count value CRn INTTMn 0000 0001 0002 0003 0004 0005 N-1 N N 0000 0001 0002 0003 n = 2, 3 9.4.3 Square-wave output operation (8-bit resolution) www..com A square wave with any selected frequency is output at intervals of the value preset to 8-bit compare register n TIOn pin output status is inverted at intervals of the count value preset to CRn by setting bit 0 (TOEn) of 8-bit timer (CRn). mode control register n (TMCn) to 1. This enables a square wave with any selected frequency to be output (duty = 50%). [Setting] <1> Set each register. * Set port latch and port mode register to 0. * TCLn: Select count clock * CRn: compare value * TMCn: Clear and start mode by match of TMn and CRn LVSn 1 0 LVRn 0 1 Timer Output F/F Status Setting High-level output Low-level output Timer output F/F inversion enabled Timer output enabled TOEn = 1 <2> After TCEn = 1 is set, count operation starts. <3> Timer output F/F is inverted by match of TMn and CRn. After INTTMn is generated, TMn is cleared to 00H. <4> Timer output F/F is inverted at the same interval and square wave is output from TIOn. Remark n = 2, 3 128 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 9.4.4 8-bit PWM output operation 8-bit timer/event counters operate as PWM output when bit 6 (TMCn6) of 8-bit timer mode control register n (TMCn) is set to 1. The duty rate pulse determined by the value set to 8-bit compare register n (CRn) is output from TIOn. Set the active level width of PWM pulse to CRn, and the active level can be selected with bit 1 (TMCn1) of TMCn. Count clock can be selected with bit 0 to bit 2 (TCLn0 to TCLn2) of timer clock select register n (TCLn). PWM output enable/disable can be selected with bit 0 (TOEn) of TMCn. Caution Rewrite of CRn in PWM mode is allowed only once in a cycle. Remark n = 2, 3 www..com (1) PWM output basic operation [Setting] <1> Set port latch (P43, P44) and port mode register 4 (PM43, PM44) to 0. <2> Set active level width with 8-bit compare register (CRn). <3> Select count clock with timer clock select register n (TCLn). <4> Set active level with bit 1 (TMCn1) of TMCn. <5> Count operation starts when bit 7 (TCEn) of TMCn is set to 1. Set TCEn to 0 to stop count operation. [PWM output operation] <1> PWM output (output from TIOn) outputs inactive level after count operation starts until overflow is generated. <2> When overflow is generated, the active level set in <1> of setting is output. The active level is output until CRn matches the count value of 8-bit counter n (TMn). <3> After the CRn matches the count value, PWM output outputs the inactive level again until overflow is generated. <4> PWM output operation <2> and <3> are repeated until the count operation stops. <5> When the count operation is stopped with TCEn = 0, PWM output changes to inactive level. Remark n = 2, 3 129 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 (a) PWM output basic operation Figure 9-8. PWM Output Operation Timing (i) Basic operation (active level = H) Count clock TMn CRn TCEn 00H 01H N FFH 00H 01H 02H N N+1 FFH 00H 01H 02H M 00H www..com INTTMn TIOn Active level Inactive level Active level (ii) CRn = 0 Count clock TMn CRn TCEn INTTMn TIOn Inactive level Inactive level 00H 01H 00H FFH 00H 01H 02H N N+1 N+2 FFH 00H 01H 02H M 00H (iii) CRn = FFH TMn CRn TCEn INTTMn TIOn 00H 01H FFH FFH 00H 01H 02H N N+1 N+2 FFH 00H 01H 02H M 00H Inactive level Active level Active level Inactive level Inactive level n = 2, 3 130 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 (b) Operation by change of CRn Figure 9-9. Timing of Operation by Change of CRn (i) Count clock TMn CRn TCEn INTTMn H N N+1 N+2 N FFH 00H 01H 02H M M M+1 M+2 FFH 00H 01H 02H M M+1 M+2 Change of CRn value to N to M before overflow of TMn www..com TIOn CRn transition (N M) (ii) Change of CRn value to N to M after overflow of TMn Count clock TMn CRn TCEn INTTMn TIOn CRn transition (N M) H N N+1 N+2 N FFH 00H 01H 02H 03H N N N+1 N+2 FFH 00H 01H 02H M M M+1 M+2 (iii) Change of CRn value to N to M between two clocks (00H and 01H) after overflow of TMn Count clock TMn CRn TCEn INTTMn TIOn CRn transition (N M) H N N+1 N+2 N FFH 00H 01H 02H N N N+1 N+2 FFH 00H 01H 02H M M M+1 M+2 n = 2, 3 131 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 9.5 8-Bit Timer/Event Counters 2 and 3 Cautions (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. This is because 8-bit counter n (TMn) is started asynchronously with the count pulse. Figure 9-10. Timer n Start Timing Count pulse TMn count value 00H Timer start 01H 02H 03H 04H www..com n = 2, 3 (2) Operation after compare register change during timer count operation If the values after the 8-bit compare register n (CRn) is changed are smaller than the value of 8-bit timer register n (TMn), TMn continues counting, overflows and then restarts counting from 0. Thus, if the value (M) after CRn change is smaller than value (N) before the change, it is necessary to restart the timer after changing CRn. Figure 9-11. Timing after Compare Register Change during Timer Count Operation Count pulse CRn TMn count value N X-1 X FFH M 00H 01H 02H Remarks 1. 2. N>X>M n = 2, 3 Caution Except when the TIOn input is selected, always set TCEn = 0 before setting the STOP state. Remark n = 2, 3 (3) TMn (n = 2, 3) reading during timer operation When TMn is read during operation, choose a select clock which has a longer high/low level wave because the select clock is stopped temporarily. 132 CHAPTER 10 WATCH TIMER 10.1 Watch Timer Functions The watch timer has the following functions. * Watch timer * Interval timer The watch timer and the interval timer can be used simultaneously. Figure 10-1 shows watch timer block diagram. www..com Figure 10-1. Watch Timer Block Diagram Selector Clear Selector 5-bit counter Clear INTWT fX/27 fX/211 fW fW 24 9-bit prescaler fW 25 fW 26 fW 27 fW 28 fW 29 Selector INTWTI WTM7 WTM6 WTM5 WTM4 WTM3 WTM1 WTM0 Watch timer mode control register (WTM) Internal bus 133 CHAPTER 10 WATCH TIMER (1) Watch timer When the main system clock is used, interrupt requests (INTWT) are generated at 0.25 second (at fX = 8.38MHz operation) intervals. (2) Interval timer Interrupt requests (INTWT) are generated at the preset time interval. Table 10-1. Interval Timer Interval Time When Operated at fX = 8.38 MHz 489 s 978 s 1.96 ms 3.91 ms 7.82 ms 15.65 ms Interval Time 212 x 1/fX www..com 213 x 1/fX 214 x 1/fX 215 x 1/fX 216 x 1/fX 217 x 1/fX Remark fX : Main system clock oscillation frequency 10.2 Watch Timer Configuration The watch timer consists of the following hardware. Table 10-2. Watch Timer Configuration Item Counter Prescaler Control register 5 bits x 1 9 bits x 1 Watch timer mode control register (WTM) Configuration 134 CHAPTER 10 WATCH TIMER 10.3 Watch Timer Control Register The watch timer mode control register (WTM) is used to control the watch timer. * Watch timer mode control register (WTM) This register sets the watch timer count clock, operation enable/disable, prescaler interval time and 5-bit counter operation control. WTM is set with an 8-bit memory manipulation instruction. RESET input clears WTM to 00H. Figure 10-2. Watch Timer Mode Control Register (WTM) Format www..com Address: FF41H Symbol WTM 7 WTM7 After Reset: 00H 6 WTM6 R/W 5 WTM5 4 WTM4 3 WTM3 2 0 1 WTM1 0 WTM0 WTM7 0 1 fX/27 (65.4 kHz) fX/211 (4.09 kHz) Watch Timer Count Clock Selection WTM6 0 0 0 0 1 1 WTM5 0 0 1 1 0 0 WTM4 0 1 0 1 0 1 24/fW 25/fW 26/fW 27/fW 28/fW (3.91 ms) (7.82 ms) (15.6 ms) (31.2 ms) (62.5 ms) Prescaler Interval Time Selection 29/fW (125 ms) Setting prohibited Other than above WTM3 0 1 WTM1 0 1 WTM0 0 1 Clear after operation stop Start Watch Flag Set Time Selection Normal operating mode (flag set at fW/214) Fast feed operating mode (flag set at fW/25) 5-bit Counter Operation Control Watch Timer Operation Control Operation stop (clear both prescaler and timer) Operation enable Remarks 1. fW : Watch timer clock frequency (fX/27 or fX/211) 2. fX : Main system clock oscillation frequency 3. Figures in parentheses apply to operation with fX = 8.38 MHz, fW = 4.09 kHz. 135 CHAPTER 10 WATCH TIMER 10.4 Watch Timer Operations 10.4.1 Watch timer operation When the 8.38-MHz main system clock is used, the timer operates as a watch timer with a 0.25-second interval. The watch timer generates interrupt requests at a constant time interval. When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer mode control register are set to 1, the count operation starts. When set to 0, the 5-bit counter is cleared and the count operation stops. For simultaneous operation of the interval timer, zero-second start can be set only for the watch timer by setting WTM1 to 0. However, since the 9-bit prescaler is not cleared the first overflow of the watch timer (INTWT) after zerosecond start may include an error of up to 29 x 1/fW. 10.4.2 Interval timer operation www..comwatch timer operates as interval timer which generates interrupt request repeatedly at an interval of the preset The count value. The interval time can be selected with bits 4 to 6 (WTM4 to WTM6) of the watch timer mode control register (WTM). Table 10-3. Interval Timer Interval Time When Operated at fW = 65.4 kHz 244 s 489 s 978 s 1.96 ms 3.91 ms 7.82 ms When Operated at fW = 4.09 kHz 3.91 ms 7.81 ms 15.6 ms 31.3 ms 62.5 ms 125 ms WTM6 0 0 0 0 1 1 WTM5 0 0 1 1 0 0 WTM4 0 1 0 1 0 1 Interval Time 24 x 1/fW 25 26 27 28 29 x 1/fW x 1/fW x 1/fW x 1/fW x 1/fW Other than above Setting prohibited Remark fW : Watch timer clock frequency 136 CHAPTER 10 WATCH TIMER Figure 10-3. Operation Timing of Watch Timer/Interval Timer 5-bit counter 0H Start Count clock fW or fW/29 Watch timer interrupt INTWT www..com Overflow Overflow Interrupt time of watch timer (0.25 s) Interrupt time of watch timer (0.25 s) Interval timer interrupt INTWTI Interval timer (T) T Remark fW : Watch timer clock frequency ( ) : fW = 4.09 kHz (fX = 8.38 MHz) 137 [MEMO] www..com 138 CHAPTER 11 WATCHDOG TIMER 11.1 Watchdog Timer Functions The watchdog timer has the following functions. * Watchdog timer * Interval timer Caution www..com Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM). Figure 11-1 shows the watchdog timer block diagram. Figure 11-1. Watchdog Timer Block Diagram RUN Internal bus fX/27 12 13 14 Prescaler Control circuit fX/2 fX/2 fX/2 fX/215 fX/216 fX/217 fX/218 fX/220 WDTMK Selector WDTIF INTWDT Maskable interrupt request RESET INTWDT Non-maskable interrupt request 3 WDCS2 WDCS1 WDCS0 Watchdog timer clock select register (WDCS) Internal bus RUN WDTM4 WDTM3 Watchdog timer mode register (WDTM) 139 CHAPTER 11 WATCHDOG TIMER (1) Watchdog timer mode A runaway is detected. Upon detection of the runaway, a non-maskable interrupt request or RESET can be generated. Table 11-1. Watchdog Timer Runaway Detection Time Runaway Detection Time 212 213 214 215 www..com 216 217 x 1/fX (489 s) x 1/fX (978 s) x 1/fX (1.96 ms) x 1/fX (3.91 ms) x 1/fX (7.82 ms) x 1/fX (15.6 ms) 218 x 1/fX (31.3 ms) 220 x 1/fX (125 ms) Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 8.38 MHz. (2) Interval timer mode Interrupt requests are generated at preset time intervals. Table 11-2. Interval Time Interval Time 212 213 214 215 216 x 1/fX (489 s) x 1/fX (978 s) x 1/fX (1.96 ms) x 1/fX (3.91 ms) x 1/fX (7.82 ms) 217 x 1/fX (15.6 ms) 218 x 1/fX (31.3 ms) 220 x 1/fX (125 ms) Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 8.38 MHz. 140 CHAPTER 11 WATCHDOG TIMER 11.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 11-3. Watchdog Timer Configuration Item Control register Configuration Watchdog timer clock select register (WDCS) Watchdog timer mode register (WDTM) 11.3 Watchdog Timer Control Registers www..com The following two types of registers are used to control the watchdog timer. * Watchdog timer clock select register (WDCS) * Watchdog timer mode register (WDTM) (1) Watchdog timer clock select register (WDCS) This register sets overflow time of the watchdog timer and the interval timer. WDCS is set with an 8-bit memory manipulation instruction. RESET input clears WDCS to 00H. Figure 11-2. Watchdog Timer Clock Select Register (WDCS) Format Address: FF42H Symbol WDCS 7 0 After Reset: 00H 6 0 R/W 5 0 4 0 3 0 2 WDCS2 1 WDCS1 0 WDCS0 WDCS2 0 0 0 0 1 1 1 1 WDCS1 0 0 1 1 0 0 1 1 WDCS0 0 1 0 1 0 1 0 1 Overflow Time of Watchdog Timer/Interval Timer 212/fX (489 s) 213/fX (978 s) 214/fX (1.96 ms) 215/fX (3.91 ms) 216/fX (7.82 ms) 217/fX (15.6 ms) 218/fX (31.3 ms) 220/fX (125 ms) Cautions 1. When rewriting WDCS to other data, stop the timer operation beforehand. 2. Bits 3 to 7 must be set to 0. Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 8.38 MHz 141 CHAPTER 11 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears WDTM to 00H. Figure 11-3. Watchdog Timer Mode Register (WDTM) Format Address: FFF9H Symbol WDTM 7 RUN RUN www..com 0 1 Count stop Counter is cleared and counting starts After Reset: 00H 6 0 R/W 5 0 4 WDTM4 3 WDTM3 2 0 1 0 0 0 Watchdog Timer Operation Mode Selection Note 1 WDTM4 0 WDTM3 x Watchdog Timer Operation Mode Selection Note 2 Interval timer mode (Maskable interrupt request occurs upon generation of an overflow) Watchdog timer mode 1 (Non-maskable interrupt request occurs upon generation of an overflow) Watchdog timer mode 2 (Reset operation is activated upon generation of an overflow) 1 0 1 1 Notes 1. Once set to 1, RUN cannot be cleared to 0 by software. Thus, once counting starts, it can only be stopped by RESET input. 2. Once set to 1, WDTM3 and WDTM4 cannot be cleared to 0 by software. Cautions 1. When 1 is set in RUN so that the watchdog timer is cleared, the actual overflow time is up to 0.5% shorter than the time set by the watchdog timer clock select register. 2. To use watchdog timer modes 1 and 2, make sure that the interrupt request flag (WDTIF) is 0, and then set WDTM4 to 1. If WDTM4 is set to 1 when WDTIF is 1, the non-maskable interrupt request occurs, regardless of the contents of WDTM3. Remark x: don't care 142 CHAPTER 11 WATCHDOG TIMER 11.4 Watchdog Timer Operations 11.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any runaways. Watchdog timer starts by setting bit 7 (RUN) of WDTM to 1. After the watchdog timer is started, set RUN to 1 within the set runaway time interval. The watchdog timer can be cleared and counting is started. If RUN is not set to 1 and the runaway detection time is past, system reset or a non-maskable interrupt request is generated according to the WDTM bit 3 (WDTM3) value. The watchdog timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set RUN to 1 before the STOP mode is set, clear the watchdog timer and then execute the STOP instruction. www..com Caution The actual runaway detection time may be shorter than the set time by a maximum of 0.5%. Table 11-4. Watchdog Timer Runaway Detection Time Runaway Detection Time 212 213 214 215 216 217 x 1/fX (489 s) x 1/fX (978 s) x 1/fX (1.96 ms) x 1/fX (3.91 ms) x 1/fX (7.82 ms) x 1/fX (15.6 ms) 218 x 1/fX (31.3 ms) 220 x 1/fX (125 ms) Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 8.38 MHz. 143 CHAPTER 11 WATCHDOG TIMER 11.4.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt request repeatedly at an interval of the preset count value when bit 3 (WDTM3) and bit 4 (WDTM4) of the watchdog timer mode register (WDTM) are set to 1 and 0, respectively. When the watchdog timer operates as interval timer, the interrupt mask flag (WDTMK) and priority specify flag (WDTPR) are validated and the maskable interrupt request (INTWDT) can be generated. Among maskable interrupts, the INTWDT default has the highest priority. The interval timer continues operating in the HALT mode but it stops in STOP mode. Thus, set RUN to 1 before the STOP mode is set, clear the interval timer and then execute the STOP instruction. Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (with the watchdog timer mode selected), the interval timer mode is not set unless RESET input is applied. www..com 2. The interval time just after setting with WDTM may be shorter than the set time by a maximum of 0.5%. Table 11-5. Interval Timer Interval Time Interval Time 212 x 1/fX (489 s) 213 x 1/fX (978 s) 214 x 1/fX (1.96 ms) 215 x 1/fX (3.91 ms) 216 x 1/fX (7.82 ms) 217 x 1/fX (15.6 ms) 218 x 1/fX (31.3 ms) 220 x 1/fX (125 ms) Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 8.38 MHz. 144 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSIs. The clock selected with the clock output selection register (CKS) is output from the PCL/SGOA/P60 pin. Figure 12-1 shows the clock output control circuit (CKU) block diagram. Figure 12-1. Clock Output Control Circuit Block Diagram www..com fX fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 SGOA Note Selector Clock control circuit PCL/SGOA/P60 3 CLOE CCS2 CCS1 CCS0 P60 output latch PM60 Port mode register 6 (PM6) Clock output selection register (CKS) Internal bus Note SGOA: Sound generator amplitude signal 12.2 Clock Output Control Circuit Configuration The clock output control circuit (CKU) consists of the following hardware. Table 12-1. Clock Output Control Circuit Configuration Item Control register Configuration Clock output selection register (CKS) Port mode register 6 (PM6) 145 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.3 Clock Output Control Circuit Control Registers The following two types of registers are used to control the CKU. * Clock output selection register (CKS) * Port mode register 6 (PM6) (1) Clock output selection register (CKS) This register sets output clock. CKS is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CKS to 00H. Figure 12-2. Clock Output Selection Register (CKS) Format www..com Address: FF40H After Reset: 00H R/W Symbol CKS 7 0 6 0 5 0 4 CLOE 3 0 2 CCS2 1 CCS1 0 CCS0 CLOE 0 1 PCL Output Enable/Disable Specification Stop clock division circuit operation. Enable clock division circuit operation. CCS2 0 0 0 0 1 1 1 1 CCS1 0 0 1 1 0 0 1 1 CCS0 0 1 0 1 0 1 0 1 fX (8.38 MHz) fX/2 (4.19 MHz) fX/22 (2.09 MHz) fX/23 (1.04 MHz) fX/24 (524 kHz) fX/25 (262 kHz) fX/26 (131 kHz) fX/27 (65.5 kHz) PCL Output Clock Selection Cautions 1. When rewriting CKS to other data, stop the timer operation beforehand. 2. Bit 3 and bits 5 to 7 must be set to 0. Remarks 1. fX = main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 8.38 MHz. 146 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT (2) Port mode register 6 (PM6) This register sets port 6 input/output in 1-bit units. When using the P60/PCL/SGOA pin for clock output, set PM60 and the output latch of P60 to 0. PM6 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM6 to FFH. Figure 12-3. Port Mode Register 6 (PM6) Format Address: FF26H After Reset: FFH R/W Symbol PM6 www..com PM6n 0 1 P6n Pin Input/Output Mode Selection (n = 0 , 1) Output mode (output buffer ON) Input mode (output buffer OFF) 7 1 6 1 5 1 4 1 3 1 2 1 1 0 PM61 PM60 147 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.4 Clock Output Control Circuit Operation 12.4.1 Clock output operation To output the clock pulse, follow the procedure described below. <1> Select the clock pulse output frequency with bits 0 to 3 (CCS0 to CCS3) of the clock output selection register (CKS) (clock pulse output in disabled status). <2> Set bit 3 (SGOB) of the sound generator control register (SGCR) to 1 (SGOF output in disabled status). <3> Set the P60 output latch to 0. <4> Set bit 0 (PM60) of port mode register 6 to 0 (set to output mode). <5> Set bit 4 (CLOE) of CKS to 1, and enable clock output. w w w Remark . D a t a S h e e t 4 . c o m The clock output control circuit is designed not to output pulses withU small width during output enable/ a disable switching of the clock output. As shown in Figure 12-4, be sure to start output from the low period of the clock (marked with * in the figure below). When stopping output, do so after securing high level of the clock. Figure 12-4. Remote Control Output Application Example CLOE * Clock output * 148 CHAPTER 13 A/D CONVERTER 13.1 A/D Converter Functions The A/D converter is an 8-bit resolution converter that converts analog inputs into digital values. It can control up to 5 analog input channels (ANI0 to ANI4). This A/D converter has the following functions: (1) A/D conversion with 8-bit resolution One channel of analog input is selected from ANI0 to ANI4, and A/D conversion is repeatedly executed with a resolution of 8 bits. Each time the conversion has been completed, interrupt request (INTAD) is generated. www..com (2) Power-fail detection function This function is to detect a voltage drop in the battery of an automobile. The result of A/D conversion (value of the ADCR1 register) and the value of PFT register (PFT: power-fail compare threshold value register) are compared. If the condition for comparison is satisfied, INTAD is generated. Figure 13-1. A/D Converter Block Diagram ANI0/P10 Selector Sample & hold circuit Voltage comparator Tap selector ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 AVREF Successive approximation register (SAR) AVSS Control circuit INTAD 3 A/D conversion result register (ADCR1) ADS12 ADS11 ADS10 Analog input channel specification register ADCS1 FR12 FR11 FR10 A/D converter mode register Internal bus 149 CHAPTER 13 A/D CONVERTER Figure 13-2. Power-Fail Detection Function Block Diagram PFCM PFEN ANI0/P10 Multiplexer Selector ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 INTAD A/D converter Comparator PFEN PFCM www..com Power-fail compare threshold value register (PFT) Power-fail compare mode register (PFM) Internal bus 13.2 A/D Converter Configuration A/D converter consists of the following hardware. Table 13-1. A/D Converter Configuration Item Analog input Register Configuration 5 channels (ANI0 to ANI4) Successive approximation register (SAR) A/D conversion result register (ADCR1) A/D converter mode register (ADM1) Analog input channel specification register (ADS1) Power-fail compare mode register (PFM) Power-fail compare threshold value register (PFT) Control register (1) Successive approximation register (SAR) This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string, and holds the result from the most significant bit (MSB). When up to the least significant bit (LSB) is set (end of A/D conversion), the SAR contents are transferred to the A/D conversion result register. (2) A/D conversion result register (ADCR1) This register holds the A/D conversion result. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register. ADCR1 is read with an 8-bit memory manipulation instruction. RESET input clears ADCR1 to 00H. Caution When write operation is executed to A/D converter mode register (ADM1) and analog input channel specification register (ADS1), the contents of ADCR1 are undefined. Read the conversion result before write operation is executed to ADM1, ADS1. If a timing other than the above is used, the correct conversion result may not be read. 150 CHAPTER 13 A/D CONVERTER (3) Sample & hold circuit The sample & hold circuit samples each analog input sequentially applied from the input circuit, and sends it to the voltage comparator. This circuit holds the sampled analog input voltage value during A/D conversion. (4) Voltage comparator The voltage comparator compares the analog input to the series resistor string output voltage. (5) Series resistor string The series resistor string is in AVREF to AVSS, and generates a voltage to be compared to the analog input. (6) ANI0 to ANI4 pins These are five analog input pins to input analog signals to undergo A/D conversion to the A/D converter. ANI0 www..com to ANI4 are alternate-function pins that can also be used for digital input. Caution Use ANI0 to ANI4 input voltages within the specification range. If a voltage higher than AVREF or lower than AVSS is applied (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. (7) AVREF pin (Shared with AVDD pin) This pin inputs the A/D converter reference voltage. This pin also functions as an analog power supply pin. Supply power to this pin when the A/D converter is used. It converts signals input to ANI0 to ANI4 into digital signals according to the voltage applied between AVREF and AVSS. The current flowing in the series resistor string can be reduced by setting the voltage to be input to the AVREF pin to AVSS level in the standby mode. (8) AVSS pin This is the GND potential pin of the A/D converter. Always keep it at the same potential as the VSS pin even when not using the A/D converter. 151 CHAPTER 13 A/D CONVERTER 13.3 A/D Converter Control Registers The following 4 types of registers are used to control A/D converter. * A/D converter mode register (ADM1) * Analog input channel specification register (ADS1) * Power-fail compare mode register (PFM) * Power-fail compare threshold value register (PFT) (1) A/D converter mode register (ADM1) This register sets the conversion time for analog input to be A/D converted, conversion start/stop and external trigger. ADM1 is set with an 8-bit memory manipulation instruction. www..com RESET input clears ADM1 to 00H. Figure 13-3. A/D Converter Mode Register (ADM1) Format Address: FF80H After Reset: 00H R/W Symbol ADM1 7 ADCS1 6 0 5 FR12 4 FR11 3 FR10 2 0 1 0 0 0 ADCS1 0 1 Stop conversion operation. A/D Conversion Operation Control Enable conversion operation. FR12 0 0 0 1 1 1 FR11 0 0 1 0 0 1 FR10 0 1 0 0 1 0 144/fX 120/fX 96/fX 288/fX 240/fX 192/fX Conversion Time Selection Note Other than above Setting prohibited Note Set so that the A/D conversion time is 19.1 s or more. Caution Bits 0 to 2 and bit 6 must be set to 0. Remark fX: Main system clock oscillation frequency 152 CHAPTER 13 A/D CONVERTER (2) Analog input channel specification register (ADS1) This register specifies the analog voltage input port for A/D conversion. ADS1 is set with an 8-bit memory manipulation instruction. RESET input clears ADS1 to 00H. Figure 13-4. Analog Input Channel Specification Register (ADS1) Format Address: FF81H After Reset: 00H R/W Symbol ADS1 7 0 6 0 5 0 4 0 3 0 2 ADS12 1 ADS11 0 ADS10 ADS12 www..com 0 0 0 0 1 ADS11 0 0 1 1 0 ADS10 0 1 0 1 0 ANI0 ANI1 ANI2 ANI3 ANI4 Analog Input Channel Specification Other than above Setting prohibited Caution Bits 3 to 7 must be set to 0. 153 CHAPTER 13 A/D CONVERTER (3) Power-fail compare mode register (PFM) The power-fail compare mode register (PFM) controls a comparison operation. RESET input clears PFM to 00H. Figure 13-5. Power-Fail Compare Mode Register (PFM) Format Address: FF82H After Reset: 00H R/W Symbol PFM 7 PFEN 6 PFCM 5 0 4 0 3 0 2 0 1 0 0 0 PFEN www..com 0 1 Enables Power-Fail Comparison Disables power-fail comparison (used as normal A/D converter) Enables power-fail comparison (used to detect power failure) PFCM 0 ADCR1 PFT ADCR1 < PFT 1 ADCR1 PFT ADCR1 < PFT Power-Fail Compare Mode Selection Generates interrupt request signal INTAD Does not generate interrupt request signal INTAD Does not generate interrupt request signal INTAD Generates interrupt request signal INTAD Caution Bits 0 to 5 must be set to 0. (4) Power-fail compare threshold value register (PFT) The power-fail compare threshold value register (PFT) sets a threshold value against which the result of A/D conversion is to be compared. PFT is set with an 8-bit memory manipulation instruction. RESET input clears PFT to 00H. 154 CHAPTER 13 A/D CONVERTER 13.4 A/D Converter Operations 13.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion with the analog input channel specification register (ADS1). <2> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the input analog voltage is held until the A/D conversion operation is ended. <4> Set bit 7 of the successive approximation register (SAR) so that the tap selector sets the series resistor string www..com voltage tap to (1/2) AVREF. <5> The voltage difference between the series resistor string voltage tap and analog input is compared with the voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB of SAR remains set. If the analog input is smaller than (1/2) AVREF, the MSB is reset. <6> Next, bit 6 of SAR is automatically set, and the operation proceeds to the next comparison. The series resistor string voltage tap is selected according to the preset value of bit 7, as described below. * Bit 7 = 1: (3/4) AVREF * Bit 7 = 0: (1/4) AVREF The voltage tap and analog input voltage are compared and bit 6 of SAR is manipulated as follows. * Analog input voltage Voltage tap: Bit 6 = 1 * Analog input voltage < Voltage tap: Bit 6 = 0 <7> Comparison is continued in this way up to bit 0 of SAR. <8> Upon completion of the comparison of 8 bits, an effective digital result value remains in SAR, and the result value is transferred to and latched in the A/D conversion result register (ADCR1). At the same time, the A/D conversion end interrupt request (INTAD) can also be generated. 155 CHAPTER 13 A/D CONVERTER Figure 13-6. Basic Operation of 8-Bit A/D Converter Conversion time Sampling time A/D converter operation Sampling A/D conversion SAR Undefined 80H C0H or 40H Conversion result www..com ADCR1 Conversion result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS1) of the A/D converter mode register (ADM1) is reset (to 0) by software. If a write operation to the ADM1 and analog input channel specification register (ADS1) is performed during an A/D conversion operation, the conversion operation is initialized, and if the ADCS1 bit is set (to 1), conversion starts again from the beginning. RESET input sets the A/D conversion result register (ADCR1) to 00H. 156 CHAPTER 13 A/D CONVERTER 13.4.2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins (ANI0 to ANI4) and the A/D conversion result (stored in the A/D conversion result register (ADCR1)) is shown by the following expression. VIN AVREF ADCR1 = INT ( or x 256 + 0.5) (ADCR1 - 0.5) x AVREF 256 VIN < (ADCR1 + 0.5) x AVREF 256 where, INT( ) VIN www..com : Function which returns integer part of value in parentheses : Analog input voltage : AVREF pin voltage AVREF ADCR1 : A/D conversion result register (ADCR1) value Figure 13-7 shows the relation between the analog input voltage and the A/D conversion result. Figure 13-7. Relation between Analog Input Voltage and A/D Conversion Result 255 254 253 A/D conversion result (ADCR1) 3 2 1 0 1 1 3 2 5 3 512 256 512 256 512 256 507 254 509 255 511 512 256 512 256 512 1 Input voltage/AVREF 157 CHAPTER 13 A/D CONVERTER 13.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One analog input channel is selected from among ANI0 to ANI4 with the analog input channel specification register (ADS1) and A/D conversion is performed. The following two types of functions can be selected by setting the PFEN flag of the PFM register. (1) Normal 8-bit A/D converter (PFEN = 0) (2) Power-fail detection function (PFEN = 1) (1) A/D conversion (when PFEN = 0) When bit 7 (ADCS1) of the A/D converter mode register (ADM1) is set to 1 and bit 7 of the power-fail compare mode register (PFM) is set to 0, A/D conversion of the voltage applied to the analog input pin specified with the analog input channel specification register (ADS1) starts. www..com Upon the end of the A/D conversion, the conversion result is stored in the A/D conversion result register (ADCR1), and the interrupt request signal (INTAD) is generated. After one A/D conversion operation is started and ended, the next conversion operation is immediately started. A/D conversion operations are repeated until new data is written to ADS1. If ADS1 is rewritten during A/D conversion operation, the A/D conversion operation under execution is stopped, and A/D conversion of a newly selected analog input channel is started. If data with ADCS1 set to 0 is written to ADM1 during A/D conversion operation, the A/D conversion operation stops immediately. (2) Power-fail detection function (when PFEN = 1) When bit 7 (ADCS1) of the A/D converter mode register (ADM1) and bit 7 (PFEN) of the power-fail compare mode register (PFM) are set to 1, A/D conversion of the voltage applied to the analog input pin specified with the analog input channel specification register (ADS1) starts. Upon the end of the A/D conversion, the conversion result is stored in the A/D conversion result register (ADCR1), compared with the value of the power-fail compare threshold value register (PFT), and INTAD is generated under the condition specified by the PFCM flag of the PFM register. Caution When executing power-fail comparison, the interrupt request signal (INTAD) is not generated on completion of the first conversion after ADCS1 has been set to 1. INTAD is valid from completion of the second conversion. 158 CHAPTER 13 A/D CONVERTER Figure 13-8. A/D Conversion ADM1 rewrite ADCS1 = 1 ADS1 rewrite ADCS1 = 0 A/D conversion ANIn ANIn ANIn ANIm ANIm Conversion suspended; Conversion results are not stored Stop ADCR1 www..com ANIn ANIn ANIm INTAD (PFEN = 0) INTAD (PFEN = 1) First conversion Condition satisfied Remarks 1. n = 0, 1, ..., 4 2. m = 0, 1, ..., 4 159 CHAPTER 13 A/D CONVERTER 13.5 A/D Converter Cautions (1) Current consumption in standby mode A/D converter stops operating in the standby mode. At this time, current consumption can be reduced by setting bit 7 (ADCS1) of the A/D converter mode register (ADM1) to 0 to stop conversion. Figure 13-9 shows how to reduce the current consumption in the standby mode. Figure 13-9. Example of Method of Reducing Current Consumption in Standby Mode AVREF www..com P-ch ADCS1 Series resistor string AVSS (2) Input range of ANI0 to ANI4 The input voltages of ANI0 to ANI4 should be within the specification range. In particular, if a voltage higher than AVREF or lower than AVSS is input (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. (3) Contending operations <1> Contention between A/D conversion result register (ADCR1) write and ADCR1 read by instruction upon the end of conversion ADCR1 read is given priority. After the read operation, the new conversion result is written to ADCR1. <2> Contention between ADCR1 write and A/D converter mode register (ADM1) write or analog input channel specification register (ADS1) write upon the end of conversion ADM1 or ADS1 write is given priority. ADCR1 write is not performed, nor is the conversion end interrupt request signal (INTAD) generated. 160 CHAPTER 13 A/D CONVERTER (4) Noise countermeasures To maintain 8-bit resolution, attention must be paid to noise input to pin AVREF and pins ANI0 to ANI4. Because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 13-10 to reduce noise. Figure 13-10. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AVREF or equal to or lower than AVSS may enter, clamp with a diode with a small VF value (0.3 V or lower). Reference voltage input AVREF www..com ANI0 to ANI4 C = 100 to 1000 pF AVSS VSS (5) ANI0 to ANI4 The analog input pins (ANI0 to ANI4) also function as input port pins (P10 to P14). When A/D conversion is performed with any of pins ANI0 to ANI4 selected, do not execute a port input instruction while conversion is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion. (6) AVREF pin input impedance A series resistor string of approximately 21 k is connected between the AVREF pin and the AVSS pin. Therefore, if the output impedance of the reference voltage is high, this will result in parallel connection to the series resistor string between the AVREF pin and the AVSS pin, and there will be a large reference voltage error. 161 CHAPTER 13 A/D CONVERTER (7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS1) is changed. Caution is therefore required since, if a change of analog input pin is performed during A/D conversion, the A/D conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ADS1 rewrite, and when ADIF is read immediately after the ADS1 rewrite, ADIF may be set despite the fact that the A/D conversion for the post-change analog input has not ended. When the A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed. Figure 13-11. A/D Conversion End Interrupt Request Generation Timing www..com ADS1 rewrite (start of ANIn conversion) ADS1 rewrite (start of ANIm conversion) ADIF is set but ANIm conversion has not ended. A/D conversion ANIn ANIn ANIm ANIm ADCR1 ANIn ANIn ANIm ANIm INTAD Remarks 1. n = 0, 1, ..., 4 2. m = 0, 1, ..., 4 (8) Read of A/D conversion result register (ADCR1) When write operation is executed to A/D converter mode register (ADM1) and analog input channel specification register (ADS1), the contents of ADCR1 are undefined. Read the conversion result before write operation is executed to ADM1, ADS1. If a timing other than the above is used, the correct conversion result may not be read. 162 CHAPTER 13 A/D CONVERTER 13.6 Cautions on Emulation (1) D/A converter mode register (DAM1) To perform debugging with an in-circuit emulator (IE-78K0-NS), the D/A converter mode register (DAM1) must be set. DAM1 is a register used to set a probe board (IE-780974-NS-EM1). DAM1 is used when the power-fail detection function is used. Unless DAM1 is set, the power-fail detection function cannot be used. DAM1 is a write-only register. Because the IE-780974-NS-EM1 uses an external analog comparator and a D/A converter to implement part of the power-fail detection function, the reference voltage must be controlled. Therefore, set bit 0 (DACE) of DAM1 to 1 when using the power-fail detection function. Figure 13-12. D/A Converter Mode Register (DAM1) Format www..com Address: FF89H After Reset: 00H W Symbol DAM1 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 DACE DACE 0 1 Disabled Reference Voltage Control Enabled (when power-fail detection function is used) Cautions 1. DAM1 is a special register that must be set when debugging is performed with an in-circuit emulator. Even if this register is used, the operation of the PD780973 Subseries is not affected. However, delete the instruction that manipulates this register from the program at the final stage of debugging. 2. Bits 7 to 1 must be set to 0. (2) A/D converter of IE-780974-NS-EM1 The A/D converter of the IE-780974-NS-EM1 may not satisfy the rating of the first A/D conversion value right after A/D conversion has been started. The above applies only to the IE-780974-NS-EM1 and does not affect the operation of the PD780973 Subseries. 163 [MEMO] www..com 164 CHAPTER 14 SERIAL INTERFACE UART 14.1 UART Functions The serial interface UART has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed to reduce power consumption. For details, see 14.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode www..com This mode enables full-duplex operation wherein one byte of data is transmitted and received after the start bit. The on-chip dedicated UART baud rate generator enables communications using a wide range of selectable baud rates. The UART baud rate generator can also be used to generate a MIDI-standard baud rate (31.25 kbps). For details, see 14.4.2 Asynchronous serial interface (UART) mode. Figure 14-1 shows the UART block diagram. Figure 14-1. UART Block Diagram Internal bus Asynchronous serial interface status register (ASIS) Receive buffer register (RXB) PE FE OVE Direction control circuit Direction control circuit 3 Transmit shift register (TXS) RxD/P53 Receive shift register (RXS) TXE Transmit control circuit INTST TxD/P54 Receive control circuit INTSER INTSR fSCK Baud rate generator fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 3 4 TXE RXE PS1 PS0 CL SL ISRM TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 Baud rate generator control register (BRGC) Asynchronous serial interface mode register (ASIM) Internal bus Selector 165 CHAPTER 14 SERIAL INTERFACE UART 14.2 UART Configuration The UART consists of the following hardware. Table 14-1. UART Configuration Item Registers Configuration Transmit shift register (TXS) Receive shift register (RXS) Receive buffer register (RXB) Asynchronous serial interface mode register (ASIM) Asynchronous serial interface status register (ASIS) Baud rate generator control register (BRGC) Control registers www..com (1) Transmit shift register (TXS) This is the register for setting transmit data. Data written to TXS is transmitted as serial data. When the data length is set as 7 bits, bits 0 to 6 of the data written to TXS are transmitted as transmit data. Writing data to TXS starts the transmit operation. TXS is written with an 8-bit memory manipulation instruction. It cannot be read. When RESET is input, its value is FFH. Caution Do not write to TXS during a transmit operation. The same address is assigned to TXS and the receive buffer register (RXB). A read operation reads values from RXB. (2) Receive shift register (RXS) This register converts serial data input via the RxD pin to parallel data. When one byte of data is received at this register, the receive data is transferred to the receive buffer register (RXB). RXS cannot be manipulated directly by a program. (3) Receive buffer register (RXB) This register is used to hold receive data. When one byte of data is received, one byte of new receive data is transferred from the receive shift register (RXS). When the data length is set as 7 bits, receive data is transferred to bits 0 to 6 of RXB. In RXB, the MSB must be set to 0. RXB is read with an 8-bit memory manipulation instruction. It cannot be written to. When RESET is input, its value is FFH. Caution The same address is assigned to RXB and the transmit shift register (TXS). During a write operation, values are written to TXS. (4) Transmit control circuit The transmit control circuit controls transmit operations, such as adding a start bit, parity bit, and stop bit to data that is written to the transmit shift register (TXS), based on the values set to the asynchronous serial interface mode register (ASIM). 166 CHAPTER 14 SERIAL INTERFACE UART (5) Receive control circuit The receive control circuit controls receive operations based on the values set to the asynchronous serial interface mode register (ASIM). During a receive operation, it performs error checking, such as for parity errors, and sets various values to the asynchronous serial interface status register (ASIS) according to the type of error that is detected. 14.3 UART Control Registers The UART uses the following three types of registers for control functions. * Asynchronous serial interface mode register (ASIM) www..com * Asynchronous serial interface status register (ASIS) * Baud rate generator control register (BRGC) (1) Asynchronous serial interface mode register (ASIM) This is an 8-bit register that controls UART's serial transfer operations. ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears the value to 00H. Figure 14-2 shows the format of ASIM. Caution In UART mode, set the port mode register (PM5X) as follows. Besides that, set all output latches to 0. * When receiving Set P53 (RXD) to the input mode (PM53 = 1) * When transmitting Set P54 (TXD) to the output mode (PM54 = 0) * When transceiving Set P53 to the input mode and P54 to the output mode 167 CHAPTER 14 SERIAL INTERFACE UART Figure 14-2. Asynchronous Serial Interface Mode Register (ASIM) Format Address: FF85H After Reset: 00H Symbol ASIM 7 TXE 6 RXE R/W 5 PS1 4 PS0 3 CL 2 SL 1 ISRM 0 0 TXE 0 0 1 1 www..com PS1 0 0 RXE 0 1 0 1 Operation stop UART mode (receive only) UART mode (transmit only) Operation Mode UART mode (transmit and receive) PS0 0 1 No parity Parity Bit Specification Zero parity always added during transmission No parity detection during reception (parity errors do not occur) 1 1 0 1 Odd parity Even parity CL 0 1 7 bits 8 bits Character Length Specification SL 0 1 1 bit 2 bits Stop Bit Length Specification for Transmit Data ISRM 0 1 Receive Completion Interrupt Control when Error Occurs Receive completion interrupt is issued when an error occurs Receive completion interrupt is not issued when an error occurs Cautions 1. Do not switch the operation mode until after the current serial transmit/receive operation has stopped. 2. Bit 0 must be set to 0. 168 CHAPTER 14 SERIAL INTERFACE UART (2) Asynchronous serial interface status register (ASIS) When a receive error occurs during UART mode, this register indicates the type of error. ASIS is read with an 8-bit memory manipulation instruction. When RESET is input, its value is 00H. Figure 14-3. Asynchronous Serial Interface Status Register (ASIS) Format Address: FF86H After Reset: 00H Symbol ASIS 7 0 6 0 R 5 0 4 0 3 0 2 PE 1 FE 0 OVE PE www..com 0 1 No parity error Parity Error Flag Parity error (Transmit data parity does not match) FE 0 1 No framing error Framing error Note 1 (Stop bit not detected) Framing Error Flag OVE 0 1 No overrun error Overrun Error Flag Overrun error Note 2 (Next receive operation was completed before data was read from receive buffer register) Notes 1. Even if a stop bit length of two bits has been set to bit 2 (SL) in the asynchronous serial interface mode register (ASIM), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. Be sure to read the contents of the receive buffer register (RXB) when an overrun error has occurred. Until the contents of RXB are read, further overrun errors will occur when receiving data. (3) Baud rate generator control register (BRGC) This register sets the serial clock for UART. BRGC is set with an 8-bit memory manipulation instruction. When RESET is input, its value is 00H. Figure 14-4 shows the format of BRGC. 169 CHAPTER 14 SERIAL INTERFACE UART Figure 14-4. Baud Rate Generator Control Register (BRGC) Format Address: FF87H After Reset: 00H Symbol BRGC 7 0 6 TPS2 R/W 5 TPS1 4 TPS0 3 MDL3 2 MDL2 1 MDL1 0 MDL0 (fX = 8.38 MHz) TPS2 0 0 0 0 www..com 1 1 1 1 TPS1 0 0 1 1 0 0 1 1 TPS0 0 1 0 1 0 1 0 1 fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 Source Clock Selection for 5-bit Counter n 1 2 3 4 5 6 7 8 MDL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MDL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MDL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MDL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Input Clock Selection for Baud Rate Generator fSCK/16 fSCK/17 fSCK/18 fSCK/19 fSCK/20 fSCK/21 fSCK/22 fSCK/23 fSCK/24 fSCK/25 fSCK/26 fSCK/27 fSCK/28 fSCK/29 fSCK/30 Setting prohibited k 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -- Cautions 1. Writing to BRGC during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. Therefore, do not write to BRGC during a communication operation. 2. Bit 7 must be set to 0. Remarks 1. fSCK : Source clock for 5-bit counter 2. n 3. k : Value set via TPS0 to TPS2 (1 n 8) : Value set via MDL0 to MDL3 (0 k 14) 170 CHAPTER 14 SERIAL INTERFACE UART 14.4 UART Operations This section explains the two modes of the UART. 14.4.1 Operation stop mode This mode is used when serial transfers are not performed to reduce power consumption. In the operation stop mode, P53/RxD and P54/TxD pins can be used as ordinary ports. (1) Register settings Operation stop mode settings are made via the asynchronous serial interface mode register (ASIM). ASIM is set with a 1-bit or 8-bit memory manipulation instruction. When RESET is input, its value is 00H. www..com Address: FF85H After Reset: 00H Symbol ASIM 7 TXE 6 RXE R/W 5 PS1 4 PS0 3 CL 2 SL 1 ISRM 0 0 TXE 0 0 RXE 0 1 Operation Mode Operation stop UART mode (receive only) RxD/P53 Pin Function Port function Serial function TxD/P54 Pin Function Port function Port function 1 0 UART mode (transmit only) UART mode (transmit and receive) Port function Serial function 1 1 Serial function Serial function Cautions 1. Do not switch the operation mode until after the current serial transmit/receive operation has stopped. 2. Bit 0 must be set to 0. 14.4.2 Asynchronous serial interface (UART) mode This mode enables full-duplex operation wherein one byte of data is transmitted or received after the start bit. The on-chip dedicated UART baud rate generator enables communications using a wide range of selectable baud rates. The UART baud rate generator can also be used to generate a MIDI-standard baud rate (31.25 kbps). (1) Register settings UART mode settings are made via the asynchronous serial interface mode register (ASIM), asynchronous serial interface status register (ASIS), and the baud rate generator control register (BRGC). 171 CHAPTER 14 SERIAL INTERFACE UART (a) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. When RESET is input, its value is 00H. Caution In UART mode, set the port mode register (PM5X) as follows. Besides that, set all output latches to 0. * When receiving Set P53 (RXD) to the input mode (PM53 = 1) * When transmitting Set P54 (TXD) to the output mode (PM54 = 0) * When transceiving Set P53 to the input mode and P54 to the output mode www..com Address: FF85H After Reset: 00H Symbol ASIM 7 TXE 6 RXE R/W 5 PS1 4 PS0 3 CL 2 SL 1 ISRM 0 0 TXE 0 0 RXE 0 1 Operation Mode Operation stop UART mode (receive only) UART mode (transmit only) UART mode (transmit and receive) RxD/P53 Pin Function Port function Serial function TxD/P54 Pin Function Port function Port function 1 0 Port function Serial function 1 1 Serial function Serial function PS1 0 0 PS0 0 1 No parity Parity Bit Specification Zero parity always added during transmission No parity detection during reception (parity errors do not occur) Odd parity Even parity 1 1 0 1 CL 0 1 7 bits 8 bits Character Length Specification SL 0 1 1 bit 2 bits Stop Bit Length Specification for Transmit Data ISRM 0 1 Receive Completion Interrupt Control when Error Occurs Receive completion interrupt is issued when an error occurs Receive completion interrupt is not issued when an error occurs Cautions 1. Do not switch the operation mode until after the current serial transmit/receive operation has stopped. 2. Bit 0 must be set to 0. 172 CHAPTER 14 SERIAL INTERFACE UART (b) Asynchronous serial interface status register (ASIS) ASIS is read with an 8-bit memory manipulation instruction. When RESET is input, its value is 00H. Address: FF86H After Reset: 00H Symbol ASIS 7 0 6 0 R 5 0 4 0 3 0 2 PE 1 FE 0 OVE PE 0 1 www..com FE 0 1 No framing error Framing error Note 1 (Stop bit not detected) No parity error Parity Error Flag Parity error (Transmit data parity does not match) Framing Error Flag OVE 0 1 No overrun error Overrun Error Flag Overrun error Note 2 (Next receive operation was completed before data was read from receive buffer register) Notes 1. Even if a stop bit length of two bits has been set to bit 2 (SL) in the asynchronous serial interface mode register (ASIM), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. Be sure to read the contents of the receive buffer register (RXB) when an overrun error has occurred. Until the contents of RXB are read, further overrun errors will occur when receiving data. 173 CHAPTER 14 SERIAL INTERFACE UART (c) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. When RESET is input, its value is 00H. Address: FF87H After Reset: 00H Symbol BRGC 7 0 6 TPS2 R/W 5 TPS1 4 TPS0 3 MDL3 2 MDL2 1 MDL1 0 MDL0 (fX = 8.38 MHz) TPS2 0 0 www..com 0 0 1 1 1 1 TPS1 0 0 1 1 0 0 1 1 TPS0 0 1 0 1 0 1 0 1 fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 Source Clock Selection for 5-bit Counter n 1 2 3 4 5 6 7 8 MDL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MDL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MDL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MDL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Input Clock Selection for Baud Rate Generator fSCK/16 fSCK/17 fSCK/18 fSCK/19 fSCK/20 fSCK/21 fSCK/22 fSCK/23 fSCK/24 fSCK/25 fSCK/26 fSCK/27 fSCK/28 fSCK/29 fSCK/30 Setting prohibited k 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -- Cautions 1. Writing to BRGC during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. Therefore, do not write to BRGC during a communication operation. 2. Bit 7 must be set to 0. Remarks 1. fSCK : Source clock for 5-bit counter 2. n 3. k : Value set via TPS0 to TPS2 (1 n 8) : Value set via MDL0 to MDL3 (0 k 14) 174 CHAPTER 14 SERIAL INTERFACE UART The transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. * Use of main system clock to generate a transmit/receive clock for baud rate The main system clock is divided to generate the transmit/receive clock. The baud rate generated by the main system clock is determined according to the following formula. fX 2n+1(k + 16) fX : Main system clock oscillation frequency n : Value set via TPS0 to TPS2 (1 n 8) www..com [Baud rate] = [Hz] For details, see Table 14-2. k : Value set via MDL0 to MDL3 (0 k 14) Table 14-2 shows the relation between the 5-bit counter's source clock assigned to bits 4 to 6 (TPS0 to TPS2) of BRGC and the "n" value in the above formula. Table 14-2. Relation between 5-bit Counter's Source Clock and "n" Value TPS2 0 0 0 0 1 1 1 1 TPS1 0 0 1 1 0 0 1 1 TPS0 0 1 0 1 0 1 0 1 fX/2 fX/22 fX/23 fX/24 fX/25 fX/26 fX/27 fX/28 5-bit Counter's Source Clock Selection n 1 2 3 4 5 6 7 8 Remark fX : Main system clock oscillation frequency (fX = 8.38 MHz) 175 CHAPTER 14 SERIAL INTERFACE UART * Error tolerance range for baud rates The tolerance range for baud rates depends on the number of bits per frame and the counter's division rate [1/(16 + k)]. Table 14-3 describes the relation between the main system clock and the baud rate and Figure 14-5 shows an example of a baud rate error tolerance range. Table 14-3. Relation between Main System Clock and Baud Rate Baud rate (bps) 600 www..com 1200 2400 4800 9600 19200 31250 38400 76800 115200 fX = 8.386 MHz BRGC Set Value 7BH 6BH 5BH 4BH 3BH 2BH 21H 1BH 0BH 01H Error (%) 1.10 1.10 1.10 1.10 1.10 -1.3 1.10 1.10 1.10 1.03 Remark fX : Main system clock oscillation frequency Figure 14-5. Error Tolerance (when k = 0) including Sampling Errors Ideal sampling point 32T 64T 256T 288T 320T 352T 304T Basic timing (clock cycle T) High-speed clock (clock cycle T') enabling normal reception Low-speed clock (clock cycle T") enabling normal reception START D0 D7 P 15.5T 336T STOP START 30.45T START D0 60.9T D0 33.55T 67.1T D7 P STOP 304.5T 15.5T Sampling error 0.5T STOP D7 301.95T P 335.5T Remark T : 5-bit counter's source clock cycle 15.5 320 x 100 = 4.8438 (%) Baud rate error tolerance (when k = 0) = 176 CHAPTER 14 SERIAL INTERFACE UART (2) Communication operations (a) Data format As shown in Figure 14-6, the format of the transmit/receive data consists of a start bit, character bits, a parity bit, and one or more stop bits. The asynchronous serial interface mode register (ASIM) is used to set the character bit length, parity selection, and stop bit length within each data frame. Figure 14-6. Format of Transmit/Receive Data in Asynchronous Serial Interface 1 data frame www..com Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit * Start bit ............. 1 bit * Character bits ... 7 bits or 8 bits * Parity bit ........... Even parity, odd parity, zero parity, or no parity * Stop bit(s) ........ 1 bit or 2 bits When "7 bits" is selected as the number of character bits, only the low-order 7 bits (bits 0 to 6) are valid, so that during a transmission the highest bit (bit 7) is ignored and during reception the highest bit (bit 7) must be set to "0". The asynchronous serial interface mode register (ASIM) and the baud rate generator control register (BRGC) are used to set the serial transfer rate. If a receive error occurs, information about the receive error can be recognized by reading the asynchronous serial interface status register (ASIS). 177 CHAPTER 14 SERIAL INTERFACE UART (b) Parity types and operations The parity bit is used to detect bit errors in transfer data. Usually, the same type of parity bit is used by the transmitting and receiving sides. When odd parity or even parity is set, errors in the parity bit (the odd-number bit) can be detected. When zero parity or no parity is set, errors are not detected. (i) Even parity * During transmission The number of bits in transmit data that includes a parity bit is controlled so that there are an even number of "1" bits. The value of the parity bit is as follows. If the transmit data contains an odd number of "1" bits : the parity bit value is "1" www..com If the transmit data contains an even number of "1" bits: the parity bit value is "0" * During reception The number of "1" bits is counted among the receive data that include a parity bit, and a parity error occurs when the result is an odd number. (ii) Odd parity * During transmission The number of bits in transmit data that includes a parity bit is controlled so that there is an odd number of "1" bits. The value of the parity bit is as follows. If the transmit data contains an odd number of "1" bits : the parity bit value is "0" If the transmit data contains an even number of "1" bits: the parity bit value is "1" * During reception The number of "1" bits is counted among the receive data that include a parity bit, and a parity error occurs when the result is an even number. (iii) Zero parity During transmission, the parity bit is set to "0" regardless of the transmit data. During reception, the parity bit is not checked. Therefore, no parity errors will occur regardless of whether the parity bit is a "0" or a "1". (iv) No parity No parity bit is added to the transmit data. During reception, receive data is regarded as having no parity bit. Since there is no parity bit, no parity errors will occur. 178 CHAPTER 14 SERIAL INTERFACE UART (c) Transmission The transmit operation is started when transmit data is written to the transmit shift register (TXS). A start bit, parity bit, and stop bit(s) are automatically added to the data. Starting the transmit operation shifts out the data in TXS, thereby emptying TXS, after which a transmit completion interrupt (INTST) is issued. The timing of the transmit completion interrupt is shown in Figure 14-7. Figure 14-7. Timing of Asynchronous Serial Interface Transmit Completion Interrupt (i) Stop bit length: 1 bit www..com TxD (output) START D0 D1 D2 D6 D7 Parity STOP INTST (ii) Stop bit length: 2 bits TxD (output) START D0 D1 D2 D6 D7 Parity STOP INTST Caution Do not rewrite the asynchronous serial interface mode register (ASIM) during a transmit operation. Rewriting to the ASIM register during a transmit operation may disable further transmit operations (in such case, enter a RESET to restore normal operation). Whether or not a transmit operation is in progress can be determined by software using the transmit completion interrupt (INTST) or the interrupt request flag (STIF) that is set by INTST. 179 CHAPTER 14 SERIAL INTERFACE UART (d) Reception The receive operation is enabled when "1" is set to bit 6 (RXE) of the asynchronous serial interface mode register (ASIM), and input via the RxD pin is sampled. The serial clock specified by ASIM is used when sampling the RxD pin. When the RxD pin goes low, the 5-bit counter begins counting and the start timing signal for data sampling is output when half of the specified baud rate time has elapsed. If sampling the RxD pin input with this start timing signal yields a low-level result, a start bit is recognized, after which the 5-bit counter is initialized and starts counting and data sampling begins. After the start bit is recognized, the character data, parity bit, and one-bit stop bit are detected, at which point reception of one data frame is completed. Once reception of one data frame is completed, the receive data in the shift register is transferred to the receive buffer register (RXB) and a receive completion interrupt (INTSR) occurs. Even if an error has occurred, the receive data in which the error occurred is still transferred to RXB. INTSR www..com occurs if bit 1 (ISRM) of ASIM is cleared to 0 on occurrence of an error. If the ISRM bit is set to 1, INTSR does not occur (see Figure 14-9). If the RXE bit is reset (to "0") during a receive operation, the receive operation is stopped immediately. At this time, the contents of RXB and ASIS do not change, nor does INTSR or INTSER occur. Figure 14-8 shows the timing of the asynchronous serial interface receive completion interrupt. Figure 14-8. Timing of Asynchronous Serial Interface Receive Completion Interrupt RxD (input) START D0 D1 D2 D6 D7 Parity STOP INTSR Caution Be sure to read the contents of the receive buffer register (RXB) even when a receive error has occurred. Overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of RXB are read. 180 CHAPTER 14 SERIAL INTERFACE UART (e) Receive errors Three types of errors can occur during a receive operation: parity error, framing error, or overrun error. If, as the result of data reception, an error flag is set to the asynchronous serial interface status register (ASIS), a receive error interrupt (INTSER) will occur. Receive error interrupts are generated before receive interrupts (INTSR). Table 14-4 lists the causes behind receive errors. As part of receive error interrupt (INTSER) servicing, the contents of ASIS can be read to determine which type of error occurred during the receive operation (see Table 14-4 and Figure 14-9). The contents of ASIS are reset (to "0") when the receive buffer register (RXB) is read or when the next data is received (if the next data contains an error, another error flag will be set). Table 14-4. Causes of Receive Errors www..com Receive Error Parity error Framing error Overrun error Cause Parity specified during transmission does not match parity of receive data Stop bit was not detected Reception of the next data was completed before data was read from the receive buffer register ASIS Value 04H 02H 01H Figure 14-9. Receive Error Timing RxD (input) START D0 D1 D2 D6 D7 Parity STOP INTSR Note INTSER (when framing/overrun error occurs) INTSER (when parity error occurs) Note If a reception error occurs when bit 1 (ISRM) of the asynchronous serial interface mode register (ASIM) is set to 1, INTSR does not occur. Cautions 1. The contents of asynchronous serial interface status register (ASIS) are reset (to "0") when the receive buffer register (RXB) is read or when the next data is received. To obtain information about the error, be sure to read the contents of ASIS before reading RXB. 2. Be sure to read the contents of the receive buffer register (RXB) even when a receive error has occurred. Overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of RXB are read. 181 [MEMO] www..com 182 CHAPTER 15 SERIAL INTERFACE SIO3 15.1 SIO3 Functions The serial interface SIO3 has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed. For details, see 15.4.1 Operation stop mode. (2) 3-wire serial I/O mode (fixed as MSB first) This is an 8-bit data transfer mode using three lines: a serial clock line (SCK), serial output line (SO), and serial www..com input line (SI). Since simultaneous transmit and receive operations are enabled in 3-wire serial I/O mode, the processing time for data transfers is reduced. The first bit in the 8-bit data in serial transfers is fixed as the MSB. 3-wire serial I/O mode is useful for connection to a peripheral I/O device that includes a clock-synchronous serial interface, a display controller, etc. For details, see 15.4.2 Three-wire serial I/O mode. Figure 15-1 shows the SIO3 block diagram. Figure 15-1. SIO3 Block Diagram Internal bus SI/P52 Serial I/O shift register (SIO) SO/P51 SCK/P50 Serial clock counter INTCSI Serial clock control circuit Selector fX/22 fX/23 fX/24 2 CSIE MODE SCL1 SCL0 Serial operation mode register (CSIM) Internal bus 183 CHAPTER 15 SERIAL INTERFACE SIO3 15.2 SIO3 Configuration The SIO3 consists of the following hardware. Table 15-1. SIO3 Configuration Item Register Control register Configuration Serial I/O shift register (SIO) Serial operation mode register (CSIM) (1) Serial I/O shift register (SIO) This is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations) www..com synchronized with the serial clock. SIO is set with an 8-bit memory manipulation instruction. When "1" is set to bit 7 (CSIE) of the serial operation mode register (CSIM), a serial operation can be started by writing data to or reading data from SIO. When transmitting, data written to SIO is output via the serial output (SO). When receiving, data is read from the serial input (SI) and written to SIO. The RESET signal resets the register value to 00H. Caution Do not access SIO during a transfer operation unless the access is triggered by a transfer start (Read is disabled when MODE = 0 and write is disabled when MODE = 1). 184 CHAPTER 15 SERIAL INTERFACE SIO3 15.3 SIO3 Control Register The SIO3 uses the following type of register for control functions. * Serial operation mode register (CSIM) (1) Serial operation mode register (CSIM) This register is used to enable or disable SIO3's serial clock, operation modes, and specific operations. CSIM is set with a 1-bit or 8-bit memory manipulation instruction. The RESET input resets the value to 00H. Caution www..com In the 3-wire serial I/O mode, set the port mode register (PM5X) as follows. Besides that, set all output latches to 0. * When serial clock output (Master transmit or Master receive) Set P50 (SCK) to the output mode (PM50 = 0) * When serial clock input (Slave transmit or Slave receive) Set P50 to the input mode (PM50 = 1) * When transmit/transceive mode Set P51 (SO) to the output mode (PM51 = 0) * When receive mode Set P52 (SI) to the input mode (PM52 = 1) Figure 15-2. Serial Operation Mode Register (CSIM) Format Address: FF84H After Reset: 00H Symbol CSIM 7 CSIE 6 0 R/W 5 0 4 0 3 0 2 MODE 1 SCL1 0 SCL0 SIO3 Operation Enable/Disable Specification CSIE Shift Register Operation 0 1 Operation disable Operation enable Transfer Operation Mode Flag MODE Operation Mode 0 1 Transmit or transmit/receive mode Receive-only mode SCL1 0 0 1 1 SCL0 0 1 0 1 External clock input fX/22 fX/23 fX/24 Clock Selection (fX = 8.38 MHz) Caution Bits 3 to 6 must be set to 0. 185 CHAPTER 15 SERIAL INTERFACE SIO3 15.4 SIO3 Operations This section explains the two modes of the SIO3. 15.4.1 Operation stop mode This mode is used when serial transfers are not performed to reduce power consumption. In the operation stop mode, the P50/SCK, P51/SO, and P52/SI pins can be used as normal I/O ports as well. (1) Register settings Operation stop mode are set via serial operation mode register (CSIM). CSIM is set with a 1-bit or 8-bit memory manipulation instruction. The RESET input resets the value to 00H. www..com Figure 15-3. Serial Operation Mode Register (CSIM) Format Address: FF84H After Reset: 00H Symbol CSIM 7 CSIE 6 0 R/W 5 0 4 0 3 0 2 MODE 1 SCL1 0 SCL0 SIO3 Operation Enable/Disable Specification CSIE Shift Register Operation 0 1 Operation disable Operation enable Caution Bits 3 to 6 must be set to 0. 186 CHAPTER 15 SERIAL INTERFACE SIO3 15.4.2 Three-wire serial I/O mode The three-wire serial I/O mode is useful when connecting a peripheral I/O device that includes a clock-synchronous serial interface, a display controller, etc. This mode executes data transfers via three lines: a serial clock line (SCK), serial output line (SO), and serial input line (SI). (1) Register settings 3-wire serial I/O mode is set via serial operation mode register (CSIM). CSIM is set with a 1-bit or 8-bit memory manipulation instruction. The RESET input resets the value to 00H. Caution www..com In the 3-wire serial I/O mode, set the port mode register (PM5X) as follows. Besides that, set all output latches to 0. * When serial clock output (Master transmit or Master receive) Set P50 (SCK) to the output mode (PM50 = 0) * When serial clock input (Slave transmit or Slave receive) Set P50 to the input mode (PM50 = 1) * When transmit/transceive mode Set P51 (SO) to the output mode (PM51 = 0) * When receive mode Set P52 (SI) to the input mode (PM52 = 1) Figure 15-4. Serial Operation Mode Register (CSIM) Format Address: FF84H After Reset: 00H Symbol CSIM 7 CSIE 6 0 R/W 5 0 4 0 3 0 2 MODE 1 SCL1 0 SCL0 SIO3 Operation Enable/Disable Specification CSIE Shift Register Operation 0 1 Operation disable Operation enable Transfer Operation Mode Flag MODE Operation Mode 0 1 Transmit or transmit/receive mode Receive-only mode SCL1 0 0 1 1 SCL0 0 1 0 1 External clock input fX/22 fX/23 fX/24 Clock Selection (fX = 8.38 MHz) Caution Bits 3 to 6 must be set to 0. 187 CHAPTER 15 SERIAL INTERFACE SIO3 (2) Communication operations In the three-wire serial I/O mode, data is transmitted and received in 8-bit units. Each bit of data is transmitted or received in synchronized with the serial clock. The serial I/O shift register (SIO) is shifted in synchronized with the falling edge of the serial clock. Transmission data is held in the SO latch and is output from the SO pin. Data that is received via the SI pin in synchronized with the rising edge of the serial clock is latched to SIO. Completion of an 8-bit transfer automatically stops operation of SIO3 and sets a serial transfer completion flag. Figure 15-5. Three-Wire Serial I/O Mode Timing Serial clock 1 DI7 DO7 2 DI6 DO6 3 DI5 DO5 4 DI4 DO4 5 DI3 DO3 6 DI2 DO2 7 DI1 DO1 8 DI0 DO0 www..com SI SO Serial transfer completion flag Transfer completion Transfer starts in synchronized with the serial clock's falling edge (3) Transfer start A serial transfer starts when the following two conditions have been satisfied and transfer data has been set to serial I/O shift register (SIO). * SIO3 operation control bit (CSIE) = 1 * After an 8-bit serial transfer, the internal serial clock is either stopped or is set to high level. * Transmit or transmit/receive mode When CSIE = 1 and MODE = 0, transfer starts when writing to SIO. * Receive-only mode When CSIE = 1 and MODE = 1, transfer starts when reading from SIO. Caution After data has been written to SIO, transfer will not start even if the CSIE bit value is set to "1". Completion of an 8-bit transfer automatically stops the serial transfer operation and sets a serial transfer completion flag. 188 CHAPTER 16 LCD CONTROLLER/DRIVER 16.1 LCD Controller/Driver Functions The functions of the LCD controller/driver incorporated in the PD780973 Subseries are shown below. (1) Automatic output of segment signals and common signals is possible by automatic reading of the display data memory. (2) Display mode * 1/4 duty (1/3 bias) (3) Any of four frame frequencies can be selected in each display mode. www..com (4) Maximum of 20 segment signal outputs (S0 to S19); 4 common signal outputs (COM0 to COM3). Fifteen of the segment signal outputs can be switched to input/output ports in units of 2 (P81/S19 to P87/S13, P90/S12 to P97/S5). The maximum number of displayable pixels is shown in Table 16-1. Table 16-1. Maximum Number of Display Pixels Bias Method 1/3 4 Time Division Common Signals Used COM0 to COM3 Maximum Number of Display Pixels 80 (20 segments x 4 commons) Note Note 10 digits on type LCD panel with 2 segments/digit. 189 CHAPTER 16 LCD CONTROLLER/DRIVER 16.2 LCD Controller/Driver Configuration The LCD controller/driver consists of the following hardware. Table 16-2. LCD Controller/Driver Configuration Item Display outputs Segment signals : 20 Configuration Dedicated segment signals: 5 Segment signal/input/output port alternate function: 14 Segment signal/input/output port/16-bit timer prescaler output alternate function: 1 Common signals : 4 (COM0 to COM3) LCD display mode register (LCDM) LCD display control register (LCDC) Control www..com registers Figure 16-1. LCD Controller/Driver Block Diagram Internal bus Display data memory FA6CH 76543210 FA68H FA67H 76543210 76543210 LCD display mode register (LCDM) FA59H 76543210 LCDON LCDM6 LCDM5 LCDM4 3 LCD clock selector fLCD 3210 selector ......... 3210 selector 3210 selector ......... 3210 selector Timing controller LCD display control register (LCDC) LCDC7 LCDC6 LCDC5 LCDC4 LIPS 4 ......... ......... Segment selector Note ............... Note Note ......... Note Common driver LCD driver voltage controller P97 output buffer P81 output buffer S0 .................. S4 S5/P97 ......... S19/P81 COM0 COM1 COM2 COM3 VLCD Note Segment driver 190 CHAPTER 16 LCD CONTROLLER/DRIVER Figure 16-2. LCD Clock Select Circuit Block Diagram fX/2 14 Prescaler fLCD/2 fLCD/2 fLCD/2 fLCD 3 2 Selector LCDCL 3 www..com LCDM6 LCDM5 LCDM4 LCD display mode register Internal bus Remarks 1. LCDCL : LCD clock 2. fLCD : LCD clock frequency 191 CHAPTER 16 LCD CONTROLLER/DRIVER 16.3 LCD Controller/Driver Control Registers The LCD controller/driver is controlled by the following two registers. * LCD display mode register (LCDM) * LCD display control register (LCDC) (1) LCD display mode register (LCDM) This register sets display operation enabling/disabling, the LCD clock, frame frequency. LCDM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears LCDM to 00H. www..com Figure 16-3. LCD Display Mode Register (LCDM) Format After Reset: 00H 7 LCDON 6 LCDM6 R/W 5 LCDM5 4 LCDM4 3 0 2 0 1 0 0 0 Address: FFB0H Symbol LCDM LCDON 0 1 LCD Display Enable/Disable Display off (all segment outputs are non-select signal outputs) Display on LCDM6 0 0 0 0 LCDM5 0 0 1 1 LCDM4 0 1 0 1 fX/217 fX/216 fX/215 fX/214 (64 Hz) LCD Clock Selection (fX = 8.38 MHz) (128 Hz) (256 Hz) (512 Hz) Other than above Setting prohibited Remark fX = Main system clock oscillation frequency 192 CHAPTER 16 LCD CONTROLLER/DRIVER (2) LCD display control register (LCDC) This register sets cutoff of the current flowing to split resistors for LCD drive voltage generation and switchover between segment output and input/output port functions. LCDC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears LCDC to 00H. Figure 16-4. LCD Display Control Register (LCDC) Format Address: FFB2H Symbol LCDC www..com LCDC7 0 0 0 0 0 0 0 0 1 Other than above LCDC6 0 0 0 0 1 1 1 1 0 LCDC5 0 0 1 1 0 0 1 1 0 LCDC4 0 1 0 1 0 1 0 1 0 7 LCDC7 After Reset: 00H 6 LCDC6 R/W 5 LCDC5 4 LCDC4 3 0 2 0 1 0 0 LIPS P81/S19 to P97/S5 Pin Functions Port Pins P81 to P97 P81 to P95 P81 to P93 P81 to P91 P81 to P87 P81 to P85 P81 to P83 P81 None Setting prohibited None S5 to S6 S5 to S8 S5 to S10 S5 to S12 S5 to S14 S5 to S16 S5 to S18 S5 to S19 Segment Pins LIPS 0 1 LCD Driving Power Supply Selection Does not supply power to LCD. Supplies power to LCD from VDD pin. Cautions 1. Pins which perform segment output cannot be used as output port pins even if 0 is set in the port mode register. 2. If a pin which performs segment output is read as a port, its value will be 0. 193 CHAPTER 16 LCD CONTROLLER/DRIVER 16.4 LCD Controller/Driver Settings LCD controller/driver settings should be performed as shown below. <1> Set the initial value in the display data memory (FA59H to FA6CH). <2> Set the pins to be used as segment outputs in the LCD display control register (LCDC). <3> Set the LCD clock in the LCD display mode register (LCDM). Next, set data in the display data memory according to the display contents. www..com 194 CHAPTER 16 LCD CONTROLLER/DRIVER 16.5 LCD Display Data Memory The LCD display data memory is mapped onto addresses FA59H to FA6CH. The data stored in the LCD display data memory can be displayed on an LCD panel by the LCD controller/driver. Figure 16-5 shows the relationship between the LCD display data memory contents and the segment outputs/ common outputs. Any area not used for display can be used as normal RAM. Figure 16-5. Relationship between LCD Display Data Memory Contents and Segment/Common Outputs Address www..com FA6CH FA6BH FA6AH FA69H b7 b6 b5 b4 b3 b2 b1 b0 S0 S1 S2 S3 FA5BH FA5AH FA59H S17/P83 S18/P82 S19/P81 COM3 COM2 COM1 COM0 Caution The higher 4 bits of the LCD display data memory do not incorporate memory. Be sure to set them to 0. 195 CHAPTER 16 LCD CONTROLLER/DRIVER 16.6 Common Signals and Segment Signals An individual pixel on an LCD panel lights when the potential difference of the corresponding common signal and segment signal reaches or exceeds a given voltage (the LCD drive voltage VLCD). The light goes off when the potential difference becomes VLCD or lower. As an LCD panel deteriorates if a DC voltage is applied in the common signals and segment signals, it is driven by AC voltage. (1) Common signals For common signals, the selection timing order is as shown in Table 16-3, and operations are repeated with these as the cycle. www..com Table 16-3. COM Signals COM signal COM0 Time division 4-time division COM1 COM2 COM3 (2) Segment signals Segment signals correspond to a 20-byte LCD display data memory (FA59H to FA6CH). Each display data memory bit 0, bit 1, bit 2, and bit 3 is read in synchronization with the COM0, COM1, COM2 and COM3 timings respectively, and if the value of the bit is 1, it is converted to the selection voltage. If the value of the bit is 0, it is converted to the non-selection voltage and output to a segment pin (S0 to S19) (S18 to S5 have an alternate function as input/output port pins). Consequently, it is necessary to check what combination of front surface electrodes (corresponding to the segment signals) and rear surface electrodes (corresponding to the common signals) of the LCD panel to be used form the display pattern, and then write bit data corresponding on a one-to-one basis with the pattern to be displayed. Bits 4 to 7 are fixed at 0. (3) Common signal and segment signal output waveforms The voltages shown in Table 16-4 are output in the common signals and segment signals. The VLCD ON voltage is only produced when the common signal and segment signal are both at the selection voltage; other combinations produce the OFF voltage. Table 16-4. LCD Drive Voltage Segment Common Select level Non-select level VLC0, VSS1 VLC2, VLC1 Select Level VSS1, VLC0 -VLCD, +VLCD -1/3VLCD, +1/3VLCD Non-Select Level VLC1, VLC2 -1/3VLCD, +1/3VLCD -1/3VLCD, +1/3VLCD 196 CHAPTER 16 LCD CONTROLLER/DRIVER Figure 16-6 shows the common signal waveform, and Figure 16-7 shows the common signal and segment signal voltages and phases. Figure 16-6. Common Signal Waveform VLC0 COMn (Divided by 4) VLC1 VLC2 VSS TF = 4 x T VLCD T: One LCDCL cycle www..com TF: Frame frequency Figure 16-7. Common Signal and Segment Signal Voltages and Phases Selected Not selected VLC0 Common signal VLC1 VLC2 VSS VLC0 VLC1 VLC2 VSS T T VLCD Segment signal VLCD T : One LCDCL cycle 197 CHAPTER 16 LCD CONTROLLER/DRIVER 16.7 Supplying LCD Drive Voltage VLC0, VLC1, and VLC2 The PD780973 Subseries have a split resistor to create an LCD drive voltage, and the drive voltage is fixed to 1/3 bias. To supply various LCD drive voltages, internal VDD or external VLCD supply voltage can be selected. Table 16-5. LCD Drive Voltage Bias Method LCD Drive Voltage VLC0 VLC1 www..com VLC2 1/3 Bias Method VLCD 2/3 VLCD 1/3 VLCD Figure 16-8 shows an example of supplying an LCD drive voltage from an internal source according to Table 16-5. By using variable resistors r1 and r2, a non-stepwise LCD drive voltage can be supplied. 198 CHAPTER 16 LCD CONTROLLER/DRIVER Figure 16-8. Example of Connection of LCD Drive Power Supply (a) To supply LCD drive voltage from VDD VDD LIPS (= 1) P-ch Open VLCD pin VLC0 R www..com VLCD VLC2 R VSS VSS VLCD = VDD VLC1 R (b) To supply LCD drive voltage from external source VDD VDD r1 LIPS (= 0) P-ch VLCD r2 VLC0 R VLC1 VLCD VLC2 R VSS VSS VLCD = 3R * r2 x VDD 3R * r2 + 3R * r1 + r1 * r2 R VSS 199 CHAPTER 16 LCD CONTROLLER/DRIVER 16.8 Display Mode 16.8.1 4-time-division display example Figure 16-10 shows the connection of a 4-time-division type 10-digit LCD panel with the display pattern shown in Figure 16-9 with the PD780973 Subseries segment signals (S0 to S19) and common signals (COM0 to COM3). The display example is "1234567890," and the display data memory contents (addresses FA59H to FA6CH) correspond to this. An explanation is given here taking the example of the 5th digit "6" ( the COM0 to COM3 common signal timings. Table 16-6. Selection and Non-Selection Voltages (COM0 to COM3) www..com Segment Common COM0 COM1 COM2 COM3 S NS S NS S S S S S8 S9 ). In accordance with the display pattern in Figure 16-9, selection and non-selection voltages must be output to pins S8 and S9 as shown in Table 16-6 at S: Selection, NS: Non-selection From this, it can be seen that 0101 must be prepared in the display data memory (address FA64H) corresponding to S8. Examples of the LCD drive waveforms between S8 and the COM0 and COM1 signals are shown in Figure 1611 (for the sake of simplicity, waveforms for COM2 and COM3 have been omitted). When S8 is at the selection voltage at the COM0 selection timing, it can be seen that the +VLCD/-VLCD AC square wave, which is the LCD illumination (ON) level, is generated. Figure 16-9. 4-Time-Division LCD Display Pattern and Electrode Connections S2n n = 0 to 9 200 , ,,,,, ,,,, , ,, , S2n + 1 COM0 COM2 ,, ,, COM1 COM3 CHAPTER 16 LCD CONTROLLER/DRIVER Figure 16-10. 4-Time-Division LCD Panel Connection Example COM3 COM2 COM1 COM0 BIT0 BIT1 BIT2 BIT3 Timing strobes FA6CH B A 9 www..com Data memory address 1 1 1 0 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 0 1 1 1 1 0 1 1 1 1 1 1 1 8 7 6 5 4 3 2 1 0 FA5FH E D C B A FA59H 1 1 1 0 0 0 1 01 11 11 1 0 1 1 1 0 1 1 0 1 1 1 111 100 010 1 1 0 0 0 0 0 0 101 0 0 0 1 01 LCD panel 1 1 0 0 0 1 1 1 1 0 0 0 201 CHAPTER 16 LCD CONTROLLER/DRIVER Figure 16-11. 4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) TF COM0 , , , , VLC0 VLC1 VLC2 VSS VLC0 COM1 www..com VLC1 VLC2 VSS VLC0 COM2 VLC1 VLC2 VSS VLC0 COM3 VLC1 VLC2 VSS VLC0 S8 VLC1 VLC2 VSS +VLCD +1/3VLCD COM0 to S8 0 -1/3VLCD -VLCD +VLCD +1/3VLCD COM1 to S8 0 -1/3VLCD -VLCD 202 CHAPTER 16 LCD CONTROLLER/DRIVER 16.9 Cautions on Emulation (1) LCD timer control register (LCDTM) To perform debugging with an in-circuit emulator (IE-78K0-NS), the LCD timer control register (LCDTM) must be set. LCDTM is a register used to set a probe board (IE-780974-NS-EM1). LCDTM is a write-only register that controls supply of the LCD clock. Unless LCDTM is set, the LCD controller/ driver does not operate. Therefore, set bit 1 (TMC21) of LCDTM to 1 when using the LCD controller/driver. Figure 16-12. LCD Timer Control Register (LCDTM) Format Address: FF4AH After Reset: 00H W Symbol www..com LCDTM 7 0 6 0 5 0 4 0 3 0 2 0 1 TMC21 0 0 TMC21 0 1 LCD Clock Supply Control LCD controller/driver stop mode (supply of LCD clock is stopped) LCD controller/driver operating mode (supply of LCD clock is enabled) Cautions 1. LCDTM is a special register that must be set when debugging is performed with an in-circuit emulator. Even if this register is used, the operation of the PD780973 Subseries is not affected. However, delete the instruction that manipulates this register from the program at the final stage of debugging. 2. Bits 7 to 2, and bit 0 must be set to 0. 203 [MEMO] www..com 204 CHAPTER 17 SOUND GENERATOR 17.1 Sound Generator Function The sound generator has the function to sound the buzzer from an external speaker, and the following two signals are output. (1) Basic cycle output signal (with/without amplitude) The signal is a buzzer signal with a variable frequency. By setting bits 0 to 2 (SGCL0 to SGCL2) of the sound generator control register (SGCR), the signal in a range of 0.25 to 7.7 kHz can be output (when fX = 8.38 MHz). The amplitude of the basic cycle output signal can be varied by ANDing the basic cycle output signal with the www..com 7-bit-resolution PWM signal, to enable control of the buzzer sound volume. (2) Amplitude output signal A PWM signal with a 7-bit resolution for variable amplitude can be independently output. Figure 17-1 shows the sound generator block diagram and Figure 17-2 shows the concept of each signal. Figure 17-1. Sound Generator Block Diagram Internal bus Sound generator control register (SGCR) TCE SGOB SGCL2 SGCL1 SGCL0 SGCL0 2 Prescaler Selector fSG1 Selector fX 1/2 fSG2 5-bit counter Clear Selector Comparator 1/2 SGO/SGOF/P61 PWM amplitude Comparator S Q R SGOB PCL/SGOA/P60 7 4 SGBR3 SGBR2 SGBR1 SGBR0 SGAM6 SGAM5 SGAM4 SGAM3 SGAM2 SGAM1 SGAM0 Sound generator amplitude register (SGAM) Internal bus P60 output latch Clock output control circuit (PCL) PM60 Port mode register 6 (PM6) Sound generator buzzer control register (SGBR) 205 CHAPTER 17 SOUND GENERATOR Figure 17-2. Concept of Each Signal Basic cycle output SGOF (without amplitude) Amplitude output SGOA Basic cycle output SGO (with amplitude) www..com 17.2 Sound Generator Configuration The sound generator consists of the following hardware. Table 17-1. Sound Generator Configuration Item Counter SG output 8 bits x 1, 5 bits x 1 SGO/SGOF (with/without append bit of basic cycle output) SGOA (amplitude output) Sound generator control register (SGCR) Sound generator buzzer control register (SGBR) Sound generator amplitude register (SGAM) Configuration Control register 206 CHAPTER 17 SOUND GENERATOR 17.3 Sound Generator Control Registers The following three types of registers are used to control the sound generator. * Sound generator control register (SGCR) * Sound generator buzzer control register (SGBR) * Sound generator amplitude register (SGAM) (1) Sound generator control register (SGCR) SGCR is a register which sets up the following four types. * Controls sound generator output www..com * Selects output of sound generator * Selects sound generator input frequency fSG1 * Selects 5-bit counter input frequency fSG2 SGCR is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SGCR to 00H. Figure 17-3 shows the SGCR format. 207 CHAPTER 17 SOUND GENERATOR Figure 17-3. Sound Generator Control Register (SGCR) Format Address: FF94H Symbol SGCR 7 TCE TCE 0 After Reset: 00H 6 0 R/W 5 0 4 0 3 SGOB 2 SGCL2 1 SGCL1 0 SGCL0 Sound Generator Operation Selection Timer operation stopped SGOF/SGO and SGOA for low-level output Sound generator operation SGOF/SGO and SGOA for output 1 www..com Caution Before setting the TCE bit, set all the other bits. Remark SGOF: Basic cycle signal (without amplitude) SGO: Basic cycle signal (with amplitude) SGOA: Amplitude signal SGOB 0 1 SGCL2 0 0 1 1 SGCL0 0 1 fSG1 = fX/2 fSG1 = fX Sound Generator Output Selection Selects SGOF and SGOA outputs Selects SGO and PCL outputs SGCL1 0 1 0 1 fSG2 = fSG1/25 5-Bit Counter Input Frequency fSG2 Selection fSG2 = fSG1/26 fSG2 = fSG1/27 fSG2 = fSG1/28 Sound Generator Input Frequency Selection Cautions 1. When rewriting SGCR to other data, stop the timer operation (TCE = 0) beforehand. 2. Bits 4 to 6 must be set to 0. 208 CHAPTER 17 SOUND GENERATOR The maximum and minimum values of the buzzer output frequency are as follows. SGCL2 SGCL1 SGCL0 fSG2 Maximum and Minimum Values of Buzzer Output fX = 8 MHz Max. (kHz) 0 0 0 0 1 1 www..com 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fSG1/26 fSG1/25 fSG1/27 fSG1/26 fSG1/28 fSG1/27 fSG1/29 fSG1/28 3.677 7.354 1.838 3.677 0.919 1.838 0.460 0.919 Min. (kHz) 1.953 3.906 0.976 1.953 0.488 0.976 0.244 0.488 fX = 8.38 MHz Max. (kHz) 3.851 7.702 1.926 0.481 0.963 1.926 0.481 0.963 Min. (kHz) 2.046 4.092 1.024 2.046 0.512 1.024 0.256 0.512 The sound generator output frequency fSG can be calculated by the following expression. fSG = 2 (SGCL0 - SGCL1 - 2 x SGCL2 - 7) x {fX/(SGBR + 17)} Substitute set 0 or 1 to SGCL0 to SGCL2 in the above expression. Substitute a decimal value to SGBR. Where fX = 8 MHz, SGCL0 to SGCL2 is (1, 0, 0), and SGBR0 to SGBR3 is (1, 1, 1, 1), SGBR = 15. Therefore, fSG = 2 (1 - 0 - 2 x 0 - 7) x {fX/(15 + 17)} = 3.906 kHz (2) Sound generator buzzer control register (SGBR) SGBR is a register that sets the basic frequency of the sound generator output signal. SGBR is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SGBR to 00H. Figure 17-4 shows the SGBR format. 209 CHAPTER 17 SOUND GENERATOR Figure 17-4. Sound Generator Buzzer Control Register (SGBR) Format Address: FF95H Symbol SGBR 7 0 After Reset: 00H 6 0 R/W 5 0 4 0 3 SGBR3 2 SGBR2 1 SGBR1 0 SGBR0 SGBR3 0 0 0 www..com 0 0 0 0 0 1 1 1 1 1 1 1 1 SGBR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SGBR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SGBR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3.677 3.472 3.290 3.125 2.976 2.841 2.717 2.604 2.500 2.404 2.315 2.232 2.155 2.083 2.016 1.953 Buzzer Output Frequency (kHz) Note fX = 8 MHz fX = 8.38 MHz 3.851 3.637 3.446 3.273 3.117 2.976 2.847 2.728 2.619 2.518 2.425 2.339 2.258 2.182 2.112 2.046 Note Output frequency where SGCL0, SGCL1, and SGCL2 are 0, 0, and 0. Cautions 1. When rewriting SGBR to other data, stop the timer operation (TCE = 0) beforehand. 2. Bits 4 to 7 must be set to 0. (3) Sound generator amplitude register (SGAM) SGAM is a register that sets the amplitude of the sound generator output signal. SGAM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SGAM to 00H. Figure 17-5 shows the SGAM format. 210 CHAPTER 17 SOUND GENERATOR Figure 17-5. Sound Generator Amplitude Register (SGAM) Format Address: FF96H Symbol SGAM 7 0 After Reset: 00H 6 SGAM6 R/W 5 SGAM5 4 SGAM4 3 SGAM3 2 SGAM2 1 SGAM1 0 SGAM0 SGAM6 0 0 0 0 www..com 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGAM5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SGAM4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SGAM3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 SGAM2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 SGAM1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 SGAM0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Amplitude 0/128 2/128 3/128 4/128 5/128 6/128 7/128 8/128 9/128 10/128 11/128 12/128 13/128 14/128 15/128 16/128 17/128 18/128 19/128 20/128 21/128 22/128 23/128 24/128 25/128 26/128 27/128 28/128 29/128 30/128 31/128 ... ... 1 1 1 1 1 1 1 128/128 Cautions 1. When rewriting the contents of SGAM, the timer operation does not need to be stopped. However, note that a high level may be output for one period due to rewrite timing. 2. Bit 7 must be set to 0. 211 CHAPTER 17 SOUND GENERATOR 17.4 Sound Generator Operations 17.4.1 To output basic cycle signal SGOF (without amplitude) Select SGOF output by setting bit 3 (SGOB) of the sound generator control register (SGCR) to "0". The basic cycle signal with a frequency specified by the SGCL0 to SGCL2 and SGBR0 to SGBR3 is output. At the same time, the amplitude signal with an amplitude specified by the SGAM0 to SGAM6 is output from the SGOA pin. Figure 17-6. Sound Generator Output Operation Timing n Timer www..com n n n n n Comparator 1 coincidence SGOF SGOA 17.4.2 To output basic cycle signal SGO (with amplitude) Select SGO output by setting bit 3 (SGOB) of the sound generator control register (SGCR) to "1". The basic cycle signal with a frequency specified by the SGCL0 to SGCL2 and SGBR0 to SGBR3 is output. When SGO output is selected, the SGOA pin can be used as a PCL output (clock output) or I/O port pin. Figure 17-7. Sound Generator Output Operation Timing n Timer n n n n n Comparator 1 coincidence SGOF SGOA SGO 212 CHAPTER 18 METER CONTROLLER/DRIVER 18.1 Meter Controller/Driver Functions The meter controller/driver is a function to drive a stepping motor for external meter control or cross coil. * Can set pulse width with a precision of 8 bits * Can set pulse width with a precision of 8 + 1 bits with 1-bit addition function * Can drive up to four 360 type meters Figure 18-1 shows the block diagram of the meter controller/driver, Figure 18-2 shows 1-bit addition circuit block www..com diagram. Figure 18-1. Meter Controller/Driver Block Diagram Internal bus Timer mode control register (MCNTC) PCS PCE Port mode control register (PMC) MODn ENn fX fX/2 Selector 8-bit timer register fCC OVF MODn ENn S Q Output control circuit SMn1 (sin+) SMn2 (sin-) Compare register (MCMPn0) 1-bit addition circuit R MODn ENn S Q Compare register (MCMPn1) Output control circuit SMn3 (cos+) SMn4 (cos-) 1-bit addition circuit R 2 2 TENn ADBn1 ADBn0 DIRn1 DIRn0 Compare control register n (MCMPCn) Internal bus Remark n = 1 to 4 213 CHAPTER 18 METER CONTROLLER/DRIVER Figure 18-2. 1-Bit Addition Circuit Block Diagram OVF S Selector Q R Compare register (MCMPnm) fCC S Q www..com 2 ADBn1 ADBn0 Compare control register (MCMPCn) Internal bus Remark n = 1 to 4, m = 0, 1 18.2 Meter Controller/Driver Configuration The meter controller/driver consists of the following hardware. Table 18-1. Meter Controller/Driver Configuration Item Timer Register Control registers Configuration Free-running up counter (MCNT): 1 channel Compare register (MCMPn1, MCMPn0): 8 channels Timer mode control register (MCNTC) Compare control register n (MCMPCn) Port mode control register (PMC) 1-bit addition circuit/output control circuit Pulse control circuit Remark n = 1 to 4 (1) Free running up counter (MCNT) MCNT is an 8-bit free running up counter, and is a register that executes increment at the rising edge of input clock. A PWM pulse with a resolution of 8 bits can be output. The duty factor can be set in a range of 0 to 100%. The count value is cleared in the following cases. * When RESET signal input * When counter stops (PCE = 0) Cautions 1. MCNT executes counting operation from 01H to FFH repeatedly. However, it counts from 00H upon operation start. 2. The PWM output is not output until the first overflow of MCNT. 214 CHAPTER 18 METER CONTROLLER/DRIVER (2) Compare register n0 (MCMPn0) MCMPn0 is an 8-bit register that can rewrite compare values through specification of bit 4 (TENn) of the compare control register n (MCMPCn). RESET input sets this register to 00H and clears hardware to 0. MCMPn0 is a register that supports read/write only for 8-bit access instructions. MCMPn0 continuously compares its value with the MCNT value. When the above two values match, a match signal of the sin side of meter n is generated. (3) Compare register n1 (MCMPn1) MCMPn1 is an 8-bit register that can rewrite compare values through specification of bit 4 (TENn) of the compare control register n (MCMPCn). RESET input sets this register to 00H and clears hardware to 0. www..com MCMPn1 is a register that supports read/write only for 8-bit access instructions. MCMPn1 continuously compares its value with the MCNT value. When the above two values match, a match signal of the cos side of meter n is generated. (4) 1-bit addition circuit The 1-bit addition circuit repeats 1-bit addition/non-addition to PWM output alternately upon MCNT overflow output, and enables the state of PWM output between current compare value and the next compare value. This circuit is controlled by bits 2 and 3 (ADBn0, ADBn1) of the MCMPCn register. (5) Output control circuit This circuit consists of a Pch and Nch drivers and can drive a meter in H bridge configuration by connecting a coil. When a meter is driven in half bridge configuration, the unused pins can be used as normal output port pins. The relation of the duty factor of the PWM signal output from the SMnm pin is indicated by the following expression (n = 1 to 4, m = 0, 1). PWM (duty) = Set value of MCMPnm x cycle of MCNT count clock 255 x cycle of MCNT count clock Set value of MCMPnm 255 x 100% = x 100% Cautions 1. MCMPn0 and MCMPn1 cannot be read or written by a 16-bit access instruction. 2. MCMPn0 and MCMPn1 are in master-slave configuration, and MCNT is compared with a slave register. The PWM pulse is not output until the first overflow occurs after the counting operation has been started because the compare data is not transferred to the slave. 215 CHAPTER 18 METER CONTROLLER/DRIVER 18.3 Meter Controller/Driver Control Registers The meter controller/driver is controlled by the following three registers. * Timer mode control register (MCNTC) * Compare control register n (MCMPCn) * Port mode control register (PMC) Remark n = 1 to 4 (1) Timer mode control register (MCNTC) MCNTC is an 8-bit register that controls the operation of the free-running up counter (MCNT). www..com MCNTC is set with an 8-bit memory manipulation instruction. RESET input clears MCNTC to 00H. Figure 18-3 shows the MCNTC format. Figure 18-3. Timer Mode Control Register (MCNTC) Format Address: FF69H Symbol MCNTC 7 0 PCS 0 1 PCE 0 1 fX fX/2 Timer Operation Control Operation stopped (timer value is cleared) Operation enabled After Reset: 00H 6 0 R/W 5 PCS 4 PCE 3 0 2 0 1 0 0 0 Timer Counter Clock Selection Cautions 1. When rewriting MCNTC to other data, stop the timer operation (PCE = 0) beforehand. 2. Bits 0 to 3, 6, and 7 must be set to 0. 216 CHAPTER 18 METER CONTROLLER/DRIVER (2) Compare control register (MCMPCn) MCMPCn is an 8-bit register that controls the operation of the compare register and output direction of the PWM pin. MCMPCn is set with an 8-bit memory manipulation instruction. RESET input clears MCMPCn to 00H. Figure 18-4 shows the MCMPCn format. Figure 18-4. Compare Control Register n (MCMPCn) Format Address: FF6BH to FF6EH Symbol MCMPCn (n = 1 to 4) www..com TENn Note 0 Enables Transfer by Register from Master to Slave Disables data transfer from master to slave. New data can be written. Transfer data from master to slave when MCNT overflows. New data cannot be written. ADBn1 0 1 ADBn0 0 1 Control of 1-bit addition circuit (cos side of meter n) No 1-bit addition to PWM output 1-bit addition to PWM output Control of 1-bit addition circuit (sin side of meter n) No 1-bit addition to PWM output 1-bit addition to PWM output 7 0 After Reset: 00H 6 0 5 0 R/W 4 TENn 3 ADBn1 2 ADBn0 1 DIRn1 0 DIRn0 1 Note TENn functions as a control bit and status flag. As soon as the timer overflows and PWM data is output, TENn is cleared to "0" by hardware. The relation among the DIRn1 and DIRn0 bits of the MCMPCn register and output pin is shown below. DIRn1 DIRn0 SMn1 Direction Control Bit SMn2 0 0 PWM PWM SMn3 PWM 0 0 PWM SMn4 0 PWM PWM 0 0 0 1 1 0 1 0 1 PWM PWM 0 0 Caution Bits 5 to 7 must be set to 0. (3) Port mode control register (PMC) PMC is an 8-bit register that specifies PWM/PORT output. PMC is set with an 8-bit memory manipulation instruction. RESET input clears PMC to 00H. Figure 18-5 shows the PMC format. 217 CHAPTER 18 METER CONTROLLER/DRIVER Figure 18-5. Port Mode Control Register (PMC) Format Address: FF6AH Symbol PMC 7 MOD4 MOD4 0 1 MOD3 www..com 0 1 MOD2 0 1 MOD1 0 1 EN4 0 1 EN3 0 1 EN2 0 1 EN1 0 1 After Reset: 00H 6 MOD3 R/W 5 MOD2 4 MOD1 3 EN4 2 EN3 1 EN2 0 EN1 Meter 4 Full/Half Bridge Selection Meter 4 output is full bridge. Meter 4 output is half bridge. Meter 3 Full/Half Bridge Selection Meter 3 output is full bridge. Meter 3 output is half bridge. Meter 2 Full/Half Bridge Selection Meter 2 output is full bridge. Meter 2 output is half bridge. Meter 1 Full/Half Bridge Selection Meter 1 output is full bridge. Meter 1 output is half bridge. Meter 4 Port/PWM Mode Selection Meter 4 output is in port mode. Meter 4 output is in PWM mode. Meter 3 Port/PWM Mode Selection Meter 3 output is in port mode. Meter 3 output is in PWM mode. Meter 2 Port/PWM Mode Selection Meter 2 output is in port mode. Meter 2 output is in PWM mode. Meter 1 Port/PWM Mode Selection Meter 1 output is in port mode. Meter 1 output is in PWM mode. 218 CHAPTER 18 METER CONTROLLER/DRIVER The relation among the ENn and MODn bits of the PMC register, DIRn1 and DIRn0 bits of the MCMPCn register, and output pins is shown below. ENn MODn x 0 0 0 0 1 1 1 1 DIRn1 x 0 0 1 1 0 0 1 1 DIRn0 x 0 1 0 1 0 1 0 1 SMn1 (sin+) PORT PWM PWM 0 0 PWM PWM PORT PORT SMn2 (sin-) PORT 0 0 PWM PWM PORT PORT PWM PWM SMn3 (cos+) PORT PWM 0 0 PWM PWM PORT PORT PWM SMn4 (cos-) PORT 0 PWM PWM 0 PORT PWM PWM PORT PWM mode half bridge Port mode PWM mode full bridge Mode 0 1 1 1 1 1 www..com 1 1 1 DIRn1 and DIRn0 mean the quadrant of sin and cos, and DIRn1, DIRn0 = 00 through 11 correspond to quadrants 1 through 4, respectively. The PWM signal is output to the specific pin of the + and - polarities of sin and cos of each quadrant. When ENn = 0, all the output pins are used as port pins regardless of MODn, DIRn1, and DIRn0. When ENn = 1 and MODn = 0, the full bridge mode is set, and 0 is output to a pin that does not output a PWM signal. When ENn = 1 and MODn = 1, the half bridge mode is set, and the pin that does not output a PWM signal is used as a port pin. Caution The output polarity of the PWM output changes when MCNT overflows. 219 CHAPTER 18 METER CONTROLLER/DRIVER 18.4 Meter Controller/Driver Operations 18.4.1 Basic operation of free-running up counter (MCNT) The free-running up counter is counted up by the count clock selected by the PCS bit of the timer mode control register. The value of MCNT is cleared by RESET input. The counting operation is enabled or disabled by the PCE bit of the timer mode control register (MCNTC). Figure 18-6 shows the timing from count start to restart. Figure 18-6. Restart Timing after Count Stop (Count StartCount StopCount Start) CLK www..com MCNT 0H 1H 2H *** N N+1 00H 1H 2H 3H 4H PCE Count Start Count Stop Count Start Remark N = 00H to FFH 18.4.2 To update PWM data Confirm that bit 4 (TENn) of MCMPCn is 0, and then set 8-bit PWM data to MCMPn1 and MCMPn0, and bits 2 and 3 (ADBn1 and ADBn0) of MCMPCn, and at the same time, set TENn to 1. The data will be automatically transferred to the slave latch when the timer overflows, and the PWM data becomes valid. At the same time, TENn is automatically cleared to 0. 220 CHAPTER 18 METER CONTROLLER/DRIVER 18.4.3 Operation of 1-bit addition circuit Figure 18-7. Timing in 1-Bit Addition Circuit Operation FFH MCNT Value 00H 01H OVF (Overflow) N www..com Match signal of expected value N PWM output of expected value N (1-bit non-addition) PWM output of expected value N (1-bit addition) PWM output of expected value N+1 (1-bit non-addition) The 1-bit addition mode repeats 1-bit addition/non-addition to PWM output alternately upon MCNT overflow output, and enables the state of PWM output between current compare value N and the next compare value N+1. In this mode, 1-bit addition to the PWM output is set by setting ADBn of the MCMPCn register to 1, and 1-bit non-addition (normal output) is set by setting ADBn to 0. Remark n = 1 to 4 221 CHAPTER 18 METER CONTROLLER/DRIVER 18.4.4 PWM output operation (output with 1 clock shifted) Figure 18-8. Timing of Output with 1 Clock Shifted Count clock Meter 1 sin (SM11, SM12) Meter 1 cos (SM13, SM14) www..com Meter 2 sin (SM21, SM22) Meter 2 cos (SM23, SM24) Meter 3 sin (SM31, SM32) Meter 3 cos (SM33, SM34) Meter 4 sin (SM41, SM42) Meter 4 cos (SM43, SM44) If the wave of sin and cos of meters 1 to 4 rises and falls internally as indicated by the broken line, the SM11 to SM44 pins always shift the count clock by 1 clock and output signals, in order to prevent VDD/GND from fluctuating. 222 CHAPTER 19 INTERRUPT FUNCTIONS 19.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in the interrupt disabled state. It does not undergo priority control and is given top priority over all other interrupt requests. A standby release signal is generated. One interrupt request from the watchdog timer is incorporated as a non-maskable interrupt. www..com (2) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specify flag registers (PR0L, PR0H, PR1L). Multiple high priority interrupts can be applied to low priority interrupts. If two or more interrupts with the same priority are simultaneously generated, each interrupt has a predetermined priority (see Table 19-1). A standby release signal is generated. Three external interrupt requests and sixteen internal interrupt requests are incorporated as maskable interrupts. (3) Software interrupt This is a vectored interrupt to be generated by executing the BRK instruction. It is acknowledged even in the interrupt disabled state. The software interrupt does not undergo interrupt priority control. 19.2 Interrupt Sources and Configuration A total of 21 interrupt sources exist among non-maskable, maskable, and software interrupts (see Table 19-1). 223 CHAPTER 19 INTERRUPT FUNCTIONS Table 19-1. Interrupt Source List Interrupt Source Name INTWDT Trigger Watchdog timer overflow (with non-maskable interrupt selected) Watchdog timer overflow (with interval timer selected) End of A/D conversion 16-bit timer overflow TI00 valid edge detection TI01 valid edge detection TI02 valid edge detection Pin input edge detection External 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H End of serial interface SIO3 transfer Generation of serial interface UART receive error End of serial interface UART reception End of serial interface UART transmission Generation of 8-bit timer register and capture register (CR1) match signal Generation of 8-bit timer register and capture register (CR2) match signal Generation of 8-bit timer register and capture register (CR3) match signal End of EEPROM write Watch timer overflow Reference time interval signal from watch timer BRK instruction execution -- Internal 0016H 0018H 001AH 001CH 001EH (B) (D) (C) Vector Table Address 0004H Basic Configuration Type Note 2 (A) Note 1 Interrupt Type Default Priority -- Internal/ External Internal Non-maskable Maskable 0 INTWDT (B) 1 2 3 www..com 4 5 6 7 8 9 10 11 12 13 INTAD INTOVF INTTM00 INTTM01 INTTM02 INTP0 INTP1 INTP2 INTCSI INTSER INTSR INTST INTTM1 14 INTTM2 0020H 15 INTTM3 0022H 16 17 18 Software -- INTWE INTWTI INTWT BRK 0024H 0026H 0028H 003EH (E) Notes 1. The default priority is the priority applicable when two or more maskable interrupt requests are generated simultaneously. 0 is the highest priority, and 18 is the lowest. 2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 19-1. 224 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Internal bus Interrupt request www..com Priority control circuit Vector table address generator Standby release signal (B) Internal maskable interrupt Internal bus MK IE PR ISP Interrupt request IF Priority control circuit Vector table address generator Standby release signal (C) External maskable interrupt (16-bit timer capture input) Internal bus Prescaler mode register (PRM0) MK IE PR ISP Interrupt request Sampling clock Edge detector IF Priority control circuit Vector table address generator Standby release signal 225 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (except 16-bit timer capture input) Internal bus External interrupt edge enable register (EGP, EGN) MK IE PR ISP www..com Interrupt request Edge detector IF Priority control circuit Vector table address generator Standby release signal (E) Software interrupt Internal bus Interrupt request Priority control circuit Vector table address generator IF : Interrupt request flag IE : Interrupt enable flag ISP : In-service priority flag MK : Interrupt mask flag PR : Priority specify flag 226 CHAPTER 19 INTERRUPT FUNCTIONS 19.3 Interrupt Function Control Registers The following 7 types of registers are used to control the interrupt functions. * Interrupt request flag register (IF0L, IF0H, IF1L) * Interrupt mask flag register (MK0L, MK0H, MK1L) * Priority specify flag register (PR0L, PR0H, PR1L) * External interrupt rising edge enable register (EGP) * External interrupt falling edge enable register (EGN) * Prescaler mode register (PRM0) * Program status word (PSW) www..com Table 19-2 gives a list of interrupt request flags, interrupt mask flags, and priority specify flags corresponding to interrupt request sources. Table 19-2. Flags Corresponding to Interrupt Request Sources Interrupt Request Flag Interrupt Source Register INTWDT INTAD INTOVF INTTM00 INTTM01 INTTM02 INTP0 INTP1 INTP2 INTCSI INTSER INTSR INTST INTTM1 INTTM2 INTTM3 INTWE INTWTI INTWT WDTIF ADIF OVFIF TMIF00 TMIF01 TMIF02 PIF0 PIF1 PIF2 CSIIF SERIF SRIF STIF TMIF1 TMIF2 TMIF3 WEIF WTIIF WTIF IF0H IF0L WDTMK ADMK OVFMK TMMK00 TMMK01 TMMK02 PMK0 PMK1 PMK2 CSIMK SERMK SRMK STMK TMMK1 TMMK2 TMMK3 WEMK WTIMK WTMK MK0H Register MK0L WDTPR ADPR OVFPR TMPR00 TMPR01 TMPR02 PPR0 PPR1 PPR2 CSIPR SERPR SRPR STPR TMPR1 TMPR2 TMPR3 WEPR WTIPR WTPR PR0H Register PR0L Interrupt Mask Flag Priority Specify Flag IF1L MK1L PR1L Remark The WDTIF, WDTMK, and WDTPR flags are interrupt control flags when the watchdog timer is used as an interval timer. 227 CHAPTER 19 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input. IF0L, IF0H, and IF1L are set with a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H are combined to form 16-bit register IF0, they are set with a 16-bit memory manipulation instruction. RESET input sets these registers to 00H. Figure 19-2. Interrupt Request Flag Register (IF0L, IF0H, IF1L) Format Address: FFE0H After Reset: 00H R/W Symbol www..com IF0L 7 PIF1 6 PIF0 5 TMIF02 4 TMIF01 3 TMIF00 2 OVFIF 1 ADIF 0 WDTIF Address: FFE1H After Reset: 00H R/W Symbol IF0H 7 TMIF3 6 TMIF2 5 TMIF1 4 STIF 3 SRIF 2 SERIF 1 CSIIF 0 PIF2 Address: FFE2H After Reset: 00H R/W Symbol IF1L 7 0 6 0 5 0 4 0 3 0 2 WTIF 1 WTIIF 0 WEIF XXIFX 0 1 Interrupt Request Flag No interrupt request signal is generated Interrupt request signal is generated, interrupt request status Cautions 1. The WDTIF flag is R/W enabled only when the watchdog timer is used as the interval timer. If watchdog timer mode 1 is used, set the WDTIF flag to 0. 2. Be sure to set 0 to IF1L bits 3 to 7. 228 CHAPTER 19 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt service. MK0L, MK0H, and MK1L are set with a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H are combined to form a 16-bit register MK0, they are set with a 16-bit memory manipulation instruction. RESET input sets these registers to FFH. Figure 19-3. Interrupt Mask Flag Register (MK0L, MK0H, MK1L) Format Address: FFE4H After Reset: FFH R/W Symbol MK0L www..com 7 PMK1 6 PMK0 5 TMMK02 4 TMMK01 3 TMMK00 2 OVFMK 1 ADMK 0 WDTMK Address: FFE5H After Reset: FFH R/W Symbol MK0H 7 TMMK3 6 TMMK2 5 TMMK1 4 STMK 3 SRMK 2 SERMK 1 CSIMK 0 PMK2 Address: FFE6H After Reset: FFH R/W Symbol MK1L 7 1 6 1 5 1 4 1 3 1 2 WTMK 1 WTIMK 0 WEMK XXMKX 0 1 Interrupt servicing enabled Interrupt servicing disabled Interrupt Servicing Control Cautions 1. If the watchdog timer is used in watchdog timer mode 1, the contents of the WDTMK flag become undefined when read. 2. Because port 0 pins have an alternate function as external interrupt request input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, 1 should be set in the interrupt mask flag before using the output mode. 3. Be sure to set 1 to MK1L bits 3 to 7. 229 CHAPTER 19 INTERRUPT FUNCTIONS (3) Priority specify flag registers (PR0L, PR0H, PR1L) The priority specify flag registers are used to set the corresponding maskable interrupt priority orders. PR0L, PR0H, and PR1L are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are combined to form 16-bit register PR0, they are set with a 16-bit memory manipulation instruction. RESET input sets these registers to FFH. Figure 19-4. Priority Specify Flag Register (PR0L, PR0H, PR1L) Format Address: FFE8H After Reset: FFH R/W Symbol PR0L 7 PPR1 6 PPR0 5 TMPR02 4 TMPR01 3 TMPR00 2 OVFPR 1 ADPR 0 WDTPR www..com Address: FFE9H After Reset: FFH R/W Symbol PR0H 7 TMPR3 6 TMPR2 5 TMPR1 4 STPR 3 SRPR 2 SERPR 1 CSIPR 0 PPR2 Address: FFEAH After Reset: FFH R/W Symbol PR1L 7 1 6 1 5 1 4 1 3 1 2 WTPR 1 WTIPR 0 WEPR XXPRX 0 1 High priority level Low priority level Priority Level Selection Cautions 1. When the watchdog timer is used in the watchdog timer mode 1, set 1 in the WDTPR flag. 2. Be sure to set 1 to PR1L bits 3 to 7. 230 CHAPTER 19 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP2. EGP and EGN are set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to 00H. Figure 19-5. External Interrupt Rising Edge Enable Register (EGP), External Interrupt Falling Edge Enable Register (EGN) Format Address: FF48H After Reset: 00H R/W Symbol EGP www..com 7 0 6 0 5 0 4 0 3 0 2 EGP2 1 EGP1 0 EGP0 Address: FF49H After Reset: 00H R/W Symbol EGN 7 0 6 0 5 0 4 0 3 0 2 EGN2 1 EGN1 0 EGN0 EGPn 0 0 1 1 EGNn 0 1 0 1 INTPn Pin Valid Edge Selection (n = 0 to 2) Interrupt disable Falling edge Rising edge Both rising and falling edges 231 CHAPTER 19 INTERRUPT FUNCTIONS (5) Prescaler mode register (PRM0) This register specifies the valid edge for TI00/P40 to TI02/P42 pins input. PRM0 is set with an 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 19-6. Prescaler Mode Register (PRM0) Format Address: FF70H After Reset: 00H R/W Symbol PRM0 7 ES21 6 ES20 5 ES11 4 ES10 3 ES01 2 ES00 1 PRM01 0 PRM00 ES21 www..com 0 0 1 1 ES20 0 1 0 1 Falling edge Rising edge Setting prohibited TI02 Valid Edge Selection Both rising and falling edges ES11 0 0 1 1 ES10 0 1 0 1 Falling edge Rising edge Setting prohibited TI01 Valid Edge Selection Both rising and falling edges ES01 0 0 1 1 ES00 0 1 0 1 Falling edge Rising edge Setting prohibited TI00 Valid Edge Selection Both rising and falling edges Caution Set the valid edge of the TI00/P40 to TI02/P42 pins after setting bit 2 of 16-bit timer mode control register 0 (TMC0) to 0 to stop the timer operation. 232 CHAPTER 19 INTERRUPT FUNCTIONS (6) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for an interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple processing are mapped. Besides 8-bit read/write, this register can carry out operations with a bit manipulation instruction and dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed, the contents of PSW are automatically saved into a stack and the IE flag is reset to 0. If a maskable interrupt request is acknowledged, the contents of the priority specify flag of the acknowledged interrupt are transferred to the ISP flag. The PSW contents are also saved into the stack with the PUSH PSW instruction. They are reset from the stack with the RETI, RETB, and POP PSW instructions. RESET input sets PSW to 02H. www..com Figure 19-7. Program Status Word Format 7 PSW IE 6 Z 5 RBS1 4 AC 3 RBS0 2 0 1 ISP 0 CY After Reset 02H Used when normal instruction is executed ISP 0 Priority of Interrupt Currently Being Serviced High-priority interrupt servicing (Low-priority interrupt disable) Interrupt request not acknowledged, or lowpriority interrupt servicing. (all maskable interrupts enable) 1 IE 0 1 Interrupt Request Acknowledge Enable/Disable Disable Enable 233 CHAPTER 19 INTERRUPT FUNCTIONS 19.4 Interrupt Servicing Operations 19.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt acknowledge disable state. It does not undergo interrupt priority control and has highest priority over all other interrupts. If a non-maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC, the IE flag and ISP flag are reset (to 0), and the contents of the vector table are loaded into PC and branched. A new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program is acknowledged after the current execution of the non-maskable interrupt servicing program is terminated (following RETI instruction execution) and one main routine instruction is executed. However, if a new non-maskable interrupt request is generated twice or more during non-maskable interrupt servicing program execution, only one nonmaskable interrupt request is acknowledged after termination of the non-maskable interrupt servicing program www..com execution. Figures 19-8, 19-9, and 19-10 show the flowchart of the non-maskable interrupt request generation through acknowledge, acknowledge timing of non-maskable interrupt request, and acknowledge operation at multiple nonmaskable interrupt request generation, respectively. 234 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-8. Non-Maskable Interrupt Request Generation to Acknowledge Flowchart Start WDTM4 = 1 (with watchdog timer mode selected)? No Interval timer Yes Overflow in WDT? No www..com Yes WDTM3 = 0 (with non-maskable interrupt selected)? No Reset processing Yes Interrupt request generation WDT interrupt servicing? Yes Interrupt control register not accessed? Yes Start of interrupt servicing WDTM: Watchdog timer mode register WDT : Watchdog timer No Interrupt request held pending No Figure 19-9. Non-Maskable Interrupt Request Acknowledge Timing PSW and PC save, jump Interrupt servicing to interrupt servicing program CPU processing Instruction Instruction WDTIF Interrupt request generated during this interval is acknowledged at WDTIF: Watchdog timer interrupt request flag . 235 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-10. Non-Maskable Interrupt Request Acknowledge Operation (a) If a non-maskable interrupt request is generated during non-maskable interrupt servicing program execution Main routine NMI request <1> NMI request <2> Execution of 1 instruction www..com Execution of NMI request <1> NMI request <2> held pending Servicing of NMI request <2> that was pended (b) If two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution Main routine NMI request <1> NMI request <2> Execution of 1 instruction NMI request <3> Execution of NMI request <1> NMI request <2> held pending NMI request <3> held pending Servicing of NMI request <2> that was pended NMI request <3> not acknowledged (Although two or more NMI requests have been generated, only one request is acknowledged.) 236 CHAPTER 19 INTERRUPT FUNCTIONS 19.4.2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt is cleared to 0. A vectored interrupt request is acknowledged if in the interrupt enable state (when IE flag is set to 1). However, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request (when the ISP flag is reset to 0). The times from generation of a maskable interrupt request until interrupt servicing is performed are listed in Table 19-3 below. For the interrupt request acknowledge timing, see the Figures 19-12 and 19-13. Table 19-3. Times from Generation of Maskable Interrupt Request until Servicing Minimum Time www..com When xxPR = 0 When xxPR = 1 7 clocks 8 clocks Maximum Time Note 32 clocks 33 clocks Note If an interrupt request is generated just before a divide instruction, the wait time becomes longer. Remark 1 clock: 1/fCPU (fCPU: CPU clock) If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specify flag is acknowledged first. If two or more interrupts requests have the same priority level, the request with the highest default priority is acknowledged first. An interrupt request that is held pending is acknowledged when it becomes acknowledgeable. Figure 19-11 shows the interrupt request acknowledge algorithm. If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of program status word (PSW), then program counter (PC), the IE flag is reset (to 0), and the contents of the priority specify flag corresponding to the acknowledged interrupt are transferred to the ISP flag. Further, the vector table data determined for each interrupt request is loaded into PC and branched. Return from an interrupt is possible with the RETI instruction. 237 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-11. Interrupt Request Acknowledge Processing Algorithm Start No xxIF = 1? Yes (Interrupt request generation) No xxMK = 0? Yes Interrupt request held pending Yes (High priority) www..com xxPR = 0? No (Low priority) Yes Any high-priority interrupt request among those simultaneously generated with xxPR = 0? Interrupt request held pending No No IE = 1? Yes Any interrupt request among those simultaneously generated with xxPR = 0? Yes No Any interrupt request among those simultaneously generated? Interrupt request held pending Yes Interrupt request held pending No Vectored interrupt servicing IE = 1? Yes ISP = 1? Yes Interrupt request held pending No Interrupt request held pending No Interrupt request held pending Vectored interrupt servicing xxIF : Interrupt request flag xxMK : Interrupt mask flag xxPR : Priority specify flag IE ISP : Flag that controls acknowledge of maskable interrupt request (1 = Enable, 0 = Disable) : Flag that indicates the priority level of the interrupt currently being serviced (0 = High-priority interrupt servicing, 1 = No interrupt request acknowledged, or low-priority interrupt servicing) 238 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-12. Interrupt Request Acknowledge Timing (Minimum Time) 6 clocks CPU processing xxIF (xxPR = 1) 8 clocks xxIF (xxPR = 0) 7 clocks www..com Instruction Instruction PSW and PC Save, Jump to interrupt servicing Interrupt servicing program Remark 1 clock: 1/fCPU (fCPU: CPU clock) Figure 19-13. Interrupt Request Acknowledge Timing (Maximum Time) 25 clocks CPU processing xxIF (xxPR = 1) 33 clocks xxIF (xxPR = 0) 32 clocks Instruction Divide instruction 6 clocks PSW and PC Save, Jump to interrupt servicing Interrupt servicing program Remark 1 clock: 1/fCPU (fCPU: CPU clock) 19.4.3 Software interrupt request acknowledge operation A software interrupt acknowledge is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (to 0), and the contents of the vector table (003EH, 003FH) are loaded into PC and branched. Return from a software interrupt is possible with the RETB instruction. Caution Do not use the RETI instruction for returning from the software interrupt. 239 CHAPTER 19 INTERRUPT FUNCTIONS 19.4.4 Multiple interrupt servicing Multiple interrupts occur when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupts do not occur unless the interrupt request acknowledge enable state is selected (IE = 1) (except non-maskable interrupts). Also, when an interrupt request is received, interrupt requests acknowledge becomes disabled (IE = 0). Therefore, to enable multiple interrupts, it is necessary to set (to 1) the IE flag with the EI instruction during interrupt servicing to enable interrupt acknowledge. Moreover, even if interrupts are enabled, multiple interrupts may not be enabled, this being subject to interrupt priority control. Two types of priority control are available: default priority control and programmable priority control. Programmable priority control is used for multiple interrupts. In the interrupt enable state, if an interrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for www..com interrupt servicing. Interrupt requests that are not enabled because of the interrupt disable state or they have multiple a lower priority are held pending. When servicing of the current interrupt ends, the pended interrupt request is acknowledged following execution of one main processing instruction execution. Multiple interrupt servicing is not possible during non-maskable interrupt servicing. Table 19-4 shows interrupt requests enabled for multiple interrupt servicing, and Figure 19-14 shows multiple interrupt examples. Table 19-4. Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing Multiple Interrupt Request Non-Maskable Interrupt Request Interrupt being Serviced Non-maskable interrupt Maskable interrupt ISP = 0 ISP = 1 Software interrupt x Maskable Interrupt Request PR = 0 IE = 1 x IE = 0 x x x x PR = 1 IE = 1 x x IE = 0 x x x x Remarks 1. : Multiple interrupt enable 2. x : Multiple interrupt disable 3. ISP and IE are flags contained in PSW. ISP = 0 : An interrupt with higher priority is being serviced. ISP = 1 : No interrupt request has been acknowledged, or an interrupt with a lower priority is being serviced. IE = 0 : Interrupt request acknowledge is disabled. IE = 1 : Interrupt request acknowledge is enabled. 4. PR is a flag contained in PR0L, PR0H, and PR1L. PR = 0 : Higher priority level PR = 1 : Lower priority level 240 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-14. Multiple Interrupt Examples (1/2) Example 1. Multiple interrupts occur twice Main processing INTxx servicing INTyy servicing INTzz servicing EI IE = 0 EI INTyy (PR = 0) IE = 0 EI INTzz (PR = 0) IE = 0 INTxx (PR = 1) RETI www..com RETI RETI During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be issued to enable interrupt request acknowledge. Example 2. Multiple interrupt servicing does not occur due to priority control Main processing INTxx servicing INTyy servicing EI IE = 0 EI INTxx (PR = 0) INTyy (PR = 1) RETI 1 instruction execution IE = 0 RETI Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower than that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. PR = 0 : Higher priority level PR = 1 : Lower priority level IE = 0 : Interrupt request acknowledge disable 241 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-14. Multiple Interrupt Examples (2/2) Example 3. Multiple interrupt servicing does not occur because interrupt is not enabled Main processing IE = 0 EI INTyy (PR = 0) RETI INTxx servicing INTyy servicing INTxx (PR = 0) www..com 1 instruction execution IE = 0 RETI Interrupt is not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt request INTyy is not acknowledged and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. PR = 0 : Higher priority level IE = 0 : Interrupt request acknowledge disable 242 CHAPTER 19 INTERRUPT FUNCTIONS 19.4.5 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is executed, request acknowledge is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below. * MOV PSW, #byte * MOV A, PSW * MOV PSW, A * MOV1 PSW.bit, CY * MOV1 CY, PSW.bit * AND1 CY, PSW.bit * OR1 CY, PSW.bit www..com * XOR1 CY, PSW.bit * SET1 PSW.bit * CLR1 PSW.bit * RETB * RETI * PUSH PSW * POP PSW * BT PSW.bit, $addr16 * BF PSW.bit, $addr16 * BTCLR PSW.bit, $addr16 * EI * DI * Manipulate instructions for the IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, PR1L, EGP, and EGN registers Caution The BRK instruction is not one of the above-listed interrupt request hold instruction. However, the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared. Therefore, even if a maskable interrupt request is generated during execution of the BRK instruction, the interrupt request is not acknowledged. However, a non-maskable interrupt request is acknowledged. The timing with which interrupt requests are held pending is shown in Figure 19-15. Figure 19-15. Interrupt Request Hold Save PSW and PC, Jump to interrupt servicing Interrupt servicing program CPU processing Instruction N Instruction M xxIF Remarks 1. Instruction N: Interrupt request hold instruction 2. Instruction M: Instruction other than interrupt request hold instruction 3. The xxPR (priority level) values do not affect the operation of xxIF (interrupt request). 243 [MEMO] www..com 244 CHAPTER 20 STANDBY FUNCTION 20.1 Standby Function and Configuration 20.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode Halt instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. The system clock oscillator continues oscillating. In this mode, current consumption is not decreased as much www..com as in the STOP mode. However, the HALT mode is effective to restart operation immediately upon interrupt request and to carry out intermittent operations such as watch operation. (2) STOP mode Stop instruction execution sets the STOP mode. In the STOP mode, the main system clock oscillator stops, stopping the whole system, thereby considerably reducing the CPU current consumption. Data memory low-voltage hold (down to VDD = 2.0 V) is possible. Thus, the STOP mode is effective to hold data memory contents with ultra-low current consumption. Because this mode can be cleared upon interrupt request, it enables intermittent operations to be carried out. However, because a wait time is required to secure an oscillation stabilization time after the STOP mode is cleared, select the HALT mode if it is necessary to start processing immediately upon interrupt request. In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set are held. The input/output port output latch and output buffer status are also held. Cautions 1. When operation is transferred to the STOP mode, be sure to stop the peripheral hardware operation and execute the STOP instruction. 2. The following sequence is recommended for power consumption reduction of the A/D converter when the standby function is used: First clear bit 7 (ADCS1) of the A/D converter mode register (ADM1) to 0 to stop the A/D conversion operation, and then execute the HALT or STOP instruction. 245 CHAPTER 20 STANDBY FUNCTION 20.1.2 Standby function control register The wait time after the STOP mode is cleared upon interrupt request is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H. Figure 20-1. Oscillation Stabilization Time Select Register (OSTS) Format Address: FFFAH After Reset: 04H R/W Symbol OSTS www..com 7 0 6 0 5 0 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0 OSTS2 0 0 0 0 1 OSTS1 0 0 1 1 0 OSTS0 0 1 0 1 0 Selection of Oscillation Stabilization Time 212/fX (488 s) 214/fX (1.95 ms) 215/fX (3.91 ms) 216/fX (7.81 ms) 217/fX (15.6 ms) Setting prohibited Other than above Caution The wait time after the STOP mode is cleared does not include the time (see "a" in the illustration below) from STOP mode clear to clock oscillation start, regardless of clearance by RESET input or by interrupt request generation. STOP mode clear X1 pin voltage waveform a VSS Remarks 1. fX: Main system clock oscillation frequency 2. Values in parentheses apply to operation with fX = 8.38 MHz. 246 CHAPTER 20 STANDBY FUNCTION 20.2 Standby Function Operations 20.2.1 HALT mode (1) HALT mode setting and operating status The HALT mode is set by executing the HALT instruction. The operating status in the HALT mode is described below. Table 20-1. HALT Mode Setting Item www..com Clock generator Main system clock can be oscillated. Clock supply to CPU stops. Operation stops. Status before HALT mode setting is held. Operable HALT Mode Operating Status During HALT Instruction Execution Using Main System Clock CPU Port (Output latch) 16-bit timer 8-bit timer Watch timer Watchdog timer A/D converter Serial interface LCD controller/driver External interrupt Sound generator Meter controller/driver Operation stops. Operable 247 CHAPTER 20 STANDBY FUNCTION (2) HALT mode clear The HALT mode can be cleared with the following three types of sources. (a) Clear upon unmasked interrupt request An unmasked interrupt request is used to clear the HALT mode. If interrupt acknowledge is enabled, vectored interrupt service is carried out. If interrupt acknowledge is disabled, the next address instruction is executed. Figure 20-2. HALT Mode Clear upon Interrupt Generation HALT instruction Standby release signal Operating mode HALT mode Oscillation Wait www..com Wait Operating mode Clock Remarks 1. The broken line indicates the case when the interrupt request which has cleared the standby mode is acknowledged. 2. Wait times are as follows: * When vectored interrupt service is carried out : 8 to 9 clocks * When vectored interrupt service is not carried out : 2 to 3 clocks (b) Clear upon non-maskable interrupt request The HALT mode is cleared and vectored interrupt service is carried out whether interrupt acknowledge is enabled or disabled. 248 CHAPTER 20 STANDBY FUNCTION (c) Clear upon RESET input As in the case with normal reset operation, a program is executed after branch to the reset vector address. Figure 20-3. HALT Mode Clear upon RESET Input Wait (217/fX: 15.6 ms) HALT instruction RESET signal Operating mode www..com HALT mode Oscillation Reset period Oscillation stop Oscillation stabilization wait status Oscillation Operating mode Clock Remarks 1. fX: Main system clock oscillation frequency 2. Values in parentheses apply to operation with fX = 8.38 MHz. Table 20-2. Clear Source Maskable interrupt request MKxx 0 0 0 0 0 1 Non-maskable interrupt request RESET input -- -- Operation after HALT Mode Clear PRxx 0 0 1 1 1 x -- -- IE 0 1 0 x 1 x x x ISP x x 1 0 1 x x x Interrupt service execution HALT mode hold Interrupt service execution Reset processing Operation Next address instruction execution Interrupt service execution Next address instruction execution x: don't care 249 CHAPTER 20 STANDBY FUNCTION 20.2.2 STOP mode (1) STOP mode setting and operating status The STOP mode is set by executing the STOP instruction. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to VDD via a pull-up resistor to minimize the leakage current at the crystal oscillator. Thus, do not use the STOP mode in a system where an external clock is used for the main system clock. 2. Because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction. After the wait set using the www..com oscillation stabilization time select register (OSTS), the operating mode is set. The operating status in the STOP mode is described below. Table 20-3. STOP Mode Setting Item Clock generator CPU Port (Output latch) 16-bit timer 8-bit timer Watch timer Watchdog timer A/D converter Serial interface Other than UART UART LCD controller/driver External interrupt Sound generator Meter controller/driver During STOP Instruction Execution Using Main System Clock Only main system clock oscillation is stopped. Operation stops. Status before STOP mode setting is held. Operation stops. Operable only when TIO2 and TIO3 are selected as count clock. Operation stops. Operation stops. Operation stops. Operable only when externally supplied input clock is specified as the serial clock. Operation stops. Operation stops. Operable Operation stops. Operation stops. STOP Mode Operating Status 250 CHAPTER 20 STANDBY FUNCTION (2) STOP mode clear The STOP mode can be cleared with the following two types of sources. (a) Clear upon unmasked interrupt request An unmasked interrupt request is used to clear the STOP mode. If interrupt acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out. If interrupt acknowledge is disabled, the next address instruction is executed. Figure 20-4. STOP Mode Clear upon Interrupt Generation Wait (Time set by OSTS) STOP instruction www..com Standby release signal Operating mode Oscillation STOP mode Oscillation stop Oscillation stabilization wait status Oscillation Operating mode Clock Remark The broken line indicates the case when the interrupt request which has cleared the standby mode is acknowledged. 251 CHAPTER 20 STANDBY FUNCTION (b) Clear upon RESET input The STOP mode is cleared and after the lapse of oscillation stabilization time, reset operation is carried out. Figure 20-5. STOP Mode Clear upon RESET Input Wait (217/fX: 15.6 ms) STOP instruction RESET signal Operating mode www..com Clock Oscillation STOP mode Oscillation stop Reset period Oscillation stabilization wait status Oscillation Operating mode Remarks 1. fX: Main system clock oscillation frequency 2. Values in parentheses apply to operation with fX = 8.38 MHz. Table 20-4. Clear Source Maskable interrupt request MKxx 0 0 0 0 0 1 RESET input -- Operation after STOP Mode Clear PRxx 0 0 1 1 1 x -- IE 0 1 0 x 1 x x ISP x x 1 0 1 x x Interrupt service execution STOP mode hold Reset processing Operation Next address instruction execution Interrupt service execution Next address instruction execution x: don't care 252 CHAPTER 21 RESET FUNCTION 21.1 Reset Function The following two operations are available to generate the reset signal. (1) (2) External reset input with RESET pin Internal reset by watchdog timer overrun time detection External reset and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input. www..com When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status shown in Table 21-1. Each pin has high impedance during reset input or during oscillation stabilization time just after reset clear. When a high level is input to the RESET pin, the reset is cleared and program execution starts after the lapse of oscillation stabilization time (217/fX). The reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization time (217/fX) (see Figures 21-2 to 214). Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin. 2. During reset input, main system clock oscillation remains stopped but subsystem clock oscillation continues. 3. When the STOP mode is cleared by reset, the STOP mode contents are held during reset input. However, the port pin becomes high-impedance. Figure 21-1. Reset Function Block Diagram RESET Reset control circuit Reset signal Count clock Watchdog timer Stop Overflow Interrupt function 253 CHAPTER 21 RESET FUNCTION Figure 21-2. Timing of Reset by RESET Input X1 Reset period (Oscillation stop) Oscillation stabilization time wait Normal operation (Reset processing) Normal operation RESET Internal reset signal Delay www..com Delay Hi-Z Port pin Figure 21-3. Timing of Reset due to Watchdog Timer Overflow X1 Reset period (Oscillation stop) Oscillation stabilization time wait Normal operation (Reset processing) Normal operation Watchdog timer overflow Internal reset signal Port pin Hi-Z Figure 21-4. Timing of Reset in STOP Mode by RESET Input X1 STOP instruction execution Normal operation RESET Stop status (Oscillation stop) Reset period (Oscillation stop) Oscillation stabilization time wait Normal operation (Reset processing) Internal reset signal Delay Port pin Delay Hi-Z 254 CHAPTER 21 RESET FUNCTION Table 21-1. Hardware Status after Reset (1/2) Hardware Program counter (PC) Note 1 Status After Reset Contents of reset vector table (0000H, 0001H) are set. Undefined 02H Stack pointer (SP) Program status word (PSW) RAM Data memory General register Port (Output latch) Port mode registers (PM0 to PM6, PM8, PM9) www..com Pull-up resistor option register (PU0) Processor clock control register (PCC) Memory size switching register (IMS) Oscillation stabilization time select register (OSTS) Oscillator mode register (OSCM) Note 3 16-bit timer TM0 Timer register (TM0) Capture registers (CR00 to CR02) Prescaler mode register (PRM0) Mode control register (TMC0) Capture pulse control register (CRC0) Undefined Note 2 Undefined Note 2 00H FFH 00H 04H CFH 04H 00H 00H 00H 00H 00H 00H Notes 1. During reset input or oscillation stabilization time wait, only the PC contents among the hardware status become undefined. All other hardware statuses remain unchanged after reset. 2. The post-reset status is held in the standby mode. 3. For PD780973(A) only. 255 CHAPTER 21 RESET FUNCTION Table 21-1. Hardware Status after Reset (2/2) Hardware 8-bit timer TM1 to TM3 Timer counters (TM1 to TM3) Compare registers (CR1 to CR3) Clock select registers (TCL1 to TCL3) Mode control registers (TMC1 to TMC3) Watch timer Watchdog timer Mode control register (WTM) Clock select register (WDCS) Mode register (WDTM) A/D converter www..com Conversion result register (ADCR1) Mode register (ADM1) Analog input channel specification register (ADS1) Power-fail compare mode register (PFM) Power-fail compare threshold value register (PFT) Serial interface UART Asynchronous serial interface mode register (ASIM) Asynchronous serial interface status register (ASIS) Baud rate generator control register (BRGC) Transmit shift register (TXS) Receive buffer register (RXB) Serial interface SIO3 Shift register (SIO) Mode register (CSIM) LCD controller/driver Display mode register (LCDM) Display control register (LCDC) EEPROM Sound generator Write control register (EEWC) Control register (SGCR) Buzzer control register (SGBR) Amplitude register (SGAM) Meter controller/driver Compare registers (MCMP10, MCMP11, MCMP20, MCMP21, MCMP30, MCMP31, MCMP40, MCMP41) Timer mode control register (MCNTC) Port mode control register (PMC) Compare control registers (MCMPC1 to MCMPC3) Interrupt Request flag registers (IF0L, IF0H, IF1L) Mask flag registers (MK0L, MK0H, MK1L) Priority specify flag registers (PR0L, PR0H, PR1L) External interrupt rising edge enable register (EGP) External interrupt falling edge enable register (EGN) 00H 00H 00H 00H 00H 00H 00H 00H 00H Status After Reset 00H 00H 00H 04H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H FFH 00H 00H 00H 00H FFH FFH 00H 00H 256 CHAPTER 22 PD78F0974 The PD78F0974 replace the internal ROM of the PD780973(A) with flash memory to which a program can be written, deleted and overwritten while mounted on a board. Table 22-1 lists the differences between the PD78F0974 and the PD780973(A). Table 22-1. Differences between PD78F0974 and PD780973(A) Item ROM type Internal ROM capacity www..com Internal high-speed RAM capacity Change of internal ROM and internal high-speed RAM capacity using memory size switching register IC pin VPP pin Electrical specifications Quality grade PD78F0974 Flash memory 32 Kbytes 1024 bytes Possible Note Mask ROM 24 Kbytes 768 bytes PD780973(A) Not provided None Available See data sheet of each product. Standard Available None Special Note Although the initial value is CFH, set the following values. IMS Setting Value 06H C8H Flash Memory 24 Kbytes 32 Kbytes Internal High-speed RAM 768 bytes 1024 bytes Remarks When using the same memory map as that of PD780973(A) When using the maximum value Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM version. 257 CHAPTER 22 PD78F0974 22.1 Memory Size Switching Register The PD78F0974 allow users to select the internal memory capacity using the memory size switching register (IMS) so that the same memory map as that of the PD780973(A) with a different size of internal memory capacity can be achieved. IMS is set by using an 8-bit memory manipulation instruction. RESET input sets IMS to CFH. Figure 22-1. Memory Size Switching Register (IMS) Format Address: FFF0H After Reset: CFH R/W Symbol www..com IMS 7 RAM2 6 RAM1 5 RAM0 4 0 3 ROM3 2 ROM2 1 ROM1 0 ROM0 RAM2 0 1 RAM1 0 1 RAM0 0 0 Internal High-Speed RAM Capacity Selection 768 bytes 1024 bytes Setting prohibited Other than above ROM3 0 1 ROM2 1 0 ROM1 1 0 ROM0 0 0 Internal ROM Capacity Selection 24 Kbytes 32 Kbytes Setting prohibited Other than above The IMS settings to obtain the same memory map as the PD780973(A) are shown in Table 22-2. Table 22-2. Memory Size Switching Register Settings Product IMS Setting 06H PD780973(A) Caution With the PD780973(A), IMS must be set to 06H. 258 CHAPTER 22 PD78F0974 22.2 Flash Memory Programming On-board writing of flash memory (with device mounted on target system) is supported. On-board writing is done after connecting a dedicated flash writer (Flashpro II) to the host machine and target system. Moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to Flashpro II. Remark Flashpro II is a product of Naitou Densei Machidaseisakusho Co., Ltd. 22.2.1 Selection of transmission method Writing to flash memory is performed using Flashpro II and serial communication. Select the transmission method www..com for writing from Table 22-3. For the selection of the transmission method, a format like the one shown in Figure 22-2 is used. The transmission methods are selected with the VPP pulse numbers shown in Table 22-3. Table 22-3. Transmission Method List Transmission Method 3-wire serial I/O Number of Channels 1 SI/P52 SO/P51 SCK/P50 RxD/P53 TxD/P54 Pseudo 3-wire serial I/O 2 P05 (serial clock input) P06 (serial data output) P07 (serial data input) P95/S7 (serial clock input) P96/S6 (serial data output) P97/S5 (serial data input) 12 Pin Used Number of VPP Pulses 0 UART 1 8 13 Cautions 1. Be sure to select the number of VPP pulses shown in Table 22-3 for the transmission method. 2. If performing write operations to flash memory with the UART transmission method, set the main system clock oscillation frequency to 4.19 MHz or higher. Figure 22-2. Transmission Method Selection Format VPP pulses 10 V VPP VDD VSS VDD RESET VSS Flash write mode 259 CHAPTER 22 PD78F0974 22.2.2 Flash memory programming function Flash memory writing is performed through command and data transmit/receive operations using the selected transmission method. The main functions are listed in Table 22-4. Table 22-4. Main Functions of Flash Memory Programming Function Reset Batch verify Batch delete Batch blank check High-speed write www..com Continuous write Status Oscillation frequency setting Delete time setting Baud rate setting Silicon signature read Description Detects write stop and transmission synchronization. Compares entire memory contents and input data. Deletes the entire memory contents. Checks the deletion status of the entire memory. Performs writing to flash memory according to write start address and number of write data (bytes). Performs successive write operations using the data input with high-speed write operation. Checks the current operation mode and operation end. Inputs the resonator oscillation frequency information. Inputs the memory delete time. Sets the transmission rate when the UART method is used. Outputs the device name, memory capacity, and device block information. 22.2.3 Flashpro II connection Connection of Flashpro II and the PD78F0974 differs depending on transmission method (3-wire serial I/O, UART, and pseudo 3-wire serial I/O). Each case of connection shows in Figures 22-3, 22-4, and 22-5. Figure 22-3. Flashpro II Connection Using 3-Wire Serial I/O Method Flashpro II VPP VDD RESET SCK SO SI GND PD78F0974 VPP VDD RESET SCK SI SO VSS 260 CHAPTER 22 PD78F0974 Figure 22-4. Flashpro II Connection Using UART Method Flashpro II VPP VDD RESET SO SI GND PD78F0974 VPP VDD RESET RxD TxD VSS www..com Figure 22-5. Flashpro II Connection Using Pseudo 3-Wire Serial I/O Method Flashpro II VPP VDD RESET SCK SO SI GND VPP VDD RESET P05, P95 (Serial clock input) P07, P97 (Serial data input) P06, P96 (Serial data output) VSS PD78F0974 261 [MEMO] www..com 262 CHAPTER 23 INSTRUCTION SET This chapter lists the instruction set of the PD780973 Subseries. For details of the operation and machine language (instruction code), refer to the separate document "78K/0 Series User's Manual--Instructions (U12326E)." www..com 263 CHAPTER 23 INSTRUCTION SET 23.1 Legend for Operation List 23.1.1 Operand identifiers and description formats Operands are described in "Operand" column of each instruction in accordance with the description format of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description formats, select one of them. Alphabetic letters in capitals and symbols, #, !, $ and [ ] are key words and must be described as they are. The meaning of the symbols are as follows. * * * * # : Immediate data ! : Absolute address $ : Relative address [ ] : Indirect address www..com In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, $, and [ ] symbols. For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description. Table 23-1. Operand Identifiers and Description Formats Identifier r rp sfr sfrp saddr saddrp addr16 addr11 addr5 word byte bit RBn Description Format X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special-function register symbol Note Special-function register symbol (16-bit manipulatable register even addresses only) Note FE20H to FF1FH Immediate data or labels FE20H to FF1FH Immediate data or labels (even addresses only) 0000H to FFFFH Immediate data or labels (Only even addresses for 16-bit data transfer instructions) 0800H to 0FFFH Immediate data or labels 0040H to 007FH Immediate data or labels (even addresses only) 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label RB0 to RB3 Note Addresses from FFD0H to FFDFH cannot be accessed with these operands. Remark For special-function register symbols, refer to Table 3-5 Special Function Register List. 264 CHAPTER 23 INSTRUCTION SET 23.1.2 Description of "operation" column A X B C D E H L AX BC DE www..com : A register; 8-bit accumulator : X register : B register : C register : D register : E register : H register : L register : AX register pair; 16-bit accumulator : BC register pair : DE register pair : HL register pair : Program counter : Stack pointer : Program status word : Carry flag : Auxiliary carry flag : Zero flag : Register bank select flag : Interrupt request enable flag : Memory contents indicated by address or register contents in parentheses : Logical product (AND) : Logical sum (OR) : Exclusive logical sum (exclusive OR) HL PC SP PSW CY AC Z RBS IE () NMIS : Non-maskable interrupt servicing flag xH, xL : Higher 8 bits and lower 8 bits of 16-bit register ---- : Inverted data addr16 : 16-bit immediate data or label jdisp8 : Signed 8-bit data (displacement value) 23.1.3 Description of "flag operation" column (Blank) : Not affected 0 1 x R : Cleared to 0 : Set to 1 : Set/cleared according to the result : Previously saved value is restored 265 CHAPTER 23 INSTRUCTION SET 23.2 Operation List Instruction Mnemonic Group Clock Operands r, #byte saddr, #byte sfr, #byte A, r r, A A, saddr saddr, A A, sfr www..com sfr, A A, !addr16 !addr16, A MOV PSW, #byte A, PSW PSW, A A, [DE] 8-bit data transfer [DE], A A, [HL] [HL], A A, [HL + byte] [HL + byte], A A, [HL + B] [HL + B], A A, [HL + C] [HL + C], A A, r A, saddr A, sfr A, !addr16 XCH A, [DE] A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Note 3 Note 3 Note 3 Flag Operation Z AC CY Byte Note 1 Note 2 2 3 3 1 1 2 2 2 2 3 3 3 2 2 1 1 1 1 2 2 1 1 1 1 1 2 2 3 1 1 2 2 2 4 6 - 2 2 4 4 - - 8 8 - - - 4 4 4 4 8 8 6 6 6 6 2 4 - 8 4 4 8 8 8 - 7 7 - - 5 5 5 5 9 9 7 5 5 5 5 5 5 9 9 7 7 7 7 - 6 6 10 r byte (saddr) byte sfr byte Ar rA A (saddr) (saddr) A A sfr sfr A A (addr16) (addr16) A PSW byte A PSW PSW A A (DE) (DE) A A (HL) (HL) A A (HL + byte) (HL + byte) A A (HL + B) (HL + B) A A (HL + C) (HL + C) A Ar A (saddr) A sfr A (addr16) A (DE) A (HL) A (HL + byte) A (HL + B) A (HL + C) x x x x x x 6 6 10 10 10 Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed. 3. Except "r = A" Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 266 CHAPTER 23 INSTRUCTION SET Instruction Mnemonic Group Clock Operands rp, #word saddrp, #word sfrp, #word AX, saddrp saddrp, AX Byte Note 1 Note 2 Flag Operation Z AC CY rp word (saddrp) word sfrp word AX (saddrp) (saddrp) AX AX sfrp sfrp AX AX rp rp AX AX (addr16) (addr16) AX AX rp A, CY A + byte (saddr), CY (saddr) + byte A, CY A + r r, CY r + A A, CY A + (saddr) A, CY A + (addr16) A, CY A + (HL) A, CY A + (HL + byte) A, CY A + (HL + B) A, CY A + (HL + C) A, CY A + byte + CY (saddr), CY (saddr) + byte + CY A, CY A + r + CY r, CY r + A + CY A, CY A + (saddr) + CY A, CY A + (addr16) + CY A, CY A + (HL) + CY A, CY A + (HL + byte) + CY A, CY A + (HL + B) + CY A, CY A + (HL + C) + CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 3 4 4 2 2 2 2 Note 3 Note 3 6 8 - 6 6 - - 4 4 10 10 4 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 - 10 10 8 8 8 8 - - 12 12 - - 8 - - 5 9 5 9 9 9 - 8 - - 5 9 5 9 9 9 16-bit data transfer MOVW AX, sfrp sfrp, AX AX, rp rp, AX 1 1 3 3 www..com AX, !addr16 !addr16, AX XCHW AX, rp A, #byte saddr, #byte A, r r, A ADD A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] 8-bit operation A, [HL + C] A, #byte saddr, #byte A, r r, A A, saddr ADDC A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Note 4 Note 4 Note 3 1 2 3 2 2 2 3 1 2 2 2 2 3 2 2 2 3 1 2 2 2 Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Only when rp = BC, DE or HL 4. Except "r = A" Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 267 CHAPTER 23 INSTRUCTION SET Instruction Mnemonic Group Clock Operands A, #byte saddr, #byte A, r r, A A, saddr Note 3 Flag Operation Z AC CY A, CY A - byte (saddr), CY (saddr) - byte A, CY A - r r, CY r - A A, CY A - (saddr) A, CY A - (addr16) A, CY A - (HL) A, CY A - (HL + byte) A, CY A - (HL + B) A, CY A - (HL + C) A, CY A - byte - CY (saddr), CY (saddr) - byte - CY A, CY A - r - CY r, CY r - A - CY A, CY A - (saddr) - CY A, CY A - (addr16) - CY A, CY A - (HL) - CY A, CY A - (HL + byte) - CY A, CY A - (HL + B) - CY A, CY A - (HL + C) - CY AA AA rr AA AA AA AA AA AA A (saddr) (addr16) (HL) (HL + byte) (HL + B) (HL + C) byte byte (saddr) (saddr) r x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Byte Note 1 Note 2 2 3 2 2 2 3 1 2 2 2 2 3 Note 3 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 - 8 - - 5 9 5 9 9 9 - 8 - - 5 9 5 9 9 9 - 8 - - 5 9 5 9 9 9 SUB A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] www..com A, [HL + C] A, #byte saddr, #byte A, r r, A 2 2 2 3 1 2 2 2 2 3 8-bit operation SUBC A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] A, #byte saddr, #byte A, r r, A Note 3 2 2 2 3 1 2 2 2 AND A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Except "r = A" Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 268 CHAPTER 23 INSTRUCTION SET Instruction Mnemonic Group Clock Operands A, #byte saddr, #byte A, r r, A A, saddr Note 3 Flag Operation Z AC CY A A byte (saddr) (saddr) byte AA r rr A A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A (HL + B) A A (HL + C) AA AA rr AA AA AA AA AA AA A - byte (saddr) - byte A-r r-A A - (saddr) A - (addr16) A - (HL) A - (HL + byte) A - (HL + B) A - (HL + C) A (saddr) (addr16) (HL) (HL + byte) (HL + B) (HL + C) byte byte (saddr) (saddr) r x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Byte Note 1 Note 2 2 3 2 2 2 3 1 2 2 2 2 3 Note 3 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 - 8 - - 5 9 5 9 9 9 - 8 - - 5 9 5 9 9 9 - 8 - - 5 9 5 9 9 9 OR A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] www..com A, [HL + C] A, #byte saddr, #byte A, r r, A 8-bit operation XOR A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] A, #byte saddr, #byte A, r r, A CMP A, saddr A, !addr16 A, [HL] A, [HL + byte] A, [HL + B] A, [HL + C] Note 3 2 2 2 3 1 2 2 2 2 3 2 2 2 3 1 2 2 2 Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed 3. Except "r = A" Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 269 CHAPTER 23 INSTRUCTION SET Instruction Mnemonic Group ADDW 16-bit operation Multiply/ divide SUBW CMPW MULU DIVUW INC Increment/ DEC decrement www..com INCW DECW ROR ROL RORC Rotate ROLC ROR4 ROL4 ADJBA ADJBS Clock Operands AX, #word AX, #word AX, #word X C r saddr r saddr rp rp A, 1 A, 1 A, 1 A, 1 [HL] [HL] Byte Note 1 Note 2 Flag Operation Z AC CY AX, CY AX + word AX, CY AX - word AX - word AX A x X AX (Quotient), C (Remainder) AX / C rr+1 (saddr) (saddr) + 1 rr-1 (saddr) (saddr) - 1 rp rp + 1 rp rp - 1 (CY, A7 A0, Am - 1 Am) x 1 time (CY, A0 A7, Am + 1 Am) x 1 time (CY A0, A7 CY, Am - 1 Am) x 1 time (CY A7, A0 CY, Am + 1 Am) x 1 time A3 - 0 (HL)3 - 0, (HL)7 - 4 A3 - 0, (HL)3 - 0 (HL)7 - 4 A3 - 0 (HL)7 - 4, (HL)3 - 0 A3 - 0, (HL)7 - 4 (HL)3 - 0 Decimal Adjust Accumulator after Addition Decimal Adjust Accumulator after Subtract CY (saddr.bit) CY sfr.bit CY A.bit CY PSW.bit CY (HL).bit (saddr.bit) CY sfr.bit CY A.bit CY PSW.bit CY (HL).bit CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 3 3 3 2 2 1 2 1 2 1 1 1 1 1 1 2 2 2 2 6 6 6 16 25 2 4 2 4 4 4 2 2 2 2 10 10 4 4 6 - 4 - 6 6 - 4 - 6 - - - - - - 6 - 6 - - - - - - 12 12 BCD adjust - - 7 7 - 7 7 8 8 - 8 8 CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit Bit manipulate CY, [HL].bit MOV1 saddr.bit, CY sfr.bit, CY A.bit, CY PSW.bit, CY [HL].bit, CY 3 3 2 3 2 3 3 2 3 2 Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 270 CHAPTER 23 INSTRUCTION SET Instruction Mnemonic Group Clock Operands CY, saddr.bit CY, sfr.bit Byte Note 1 Note 2 Flag Operation Z AC CY CY CY CY CY CY CY CY CY CY CY (saddr.bit) sfr.bit A.bit PSW.bit (HL).bit x x x x x x x x x x x x x x x 3 3 2 3 2 3 3 2 3 2 3 3 2 3 2 2 3 2 2 2 2 3 2 2 2 1 1 1 6 - 4 - 6 6 - 4 - 6 6 - 4 - 6 4 - 4 - 6 4 - 4 - 6 2 2 2 7 7 - 7 7 7 7 - 7 7 7 7 - 7 7 6 8 - 6 8 6 8 - 6 8 - - - AND1 CY, A.bit CY, PSW.bit CY, [HL].bit CY, saddr.bit CY, sfr.bit CY CY (saddr.bit) CY CY sfr.bit CY CY A.bit CY CY PSW.bit CY CY (HL).bit CY CY CY CY CY CY CY CY CY CY sfr.bit 1 A.bit 1 PSW.bit 1 (HL).bit 1 (saddr.bit) 0 sfr.bit 0 A.bit 0 PSW.bit 0 (HL).bit 0 CY 1 CY 0 CY CY x x x x (saddr.bit) sfr.bit A.bit PSW.bit (HL).bit OR1 CY, A.bit CY, PSW.bit www..com CY, [HL].bit CY, saddr.bit CY, sfr.bit Bit manipulate XOR1 CY, A.bit CY, PSW.bit CY, [HL].bit saddr.bit sfr.bit SET1 A.bit PSW.bit [HL].bit saddr.bit sfr.bit CLR1 A.bit PSW.bit [HL].bit SET1 CLR1 NOT1 CY CY CY (saddr.bit) 1 x x 1 0 x Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 271 CHAPTER 23 INSTRUCTION SET Instruction Mnemonic Group CALL Clock Operands Byte Note 1 Note 2 Flag Operation Z AC CY (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 (SP - 1) (PC + 2)H, (SP - 2) (PC + 2)L, PC15 - 11 00001, PC10 - 0 addr11, SP SP - 2 (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 (SP - 1) PSW, (SP - 2) (PC + 1)H, (SP - 3) (PC + 1)L, PCH (003FH), PCL (003EH), SP SP - 3, IE 0 PCH (SP + 1), PCL (SP), SP SP + 2 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3, NMIS 0 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3 (SP - 1) PSW, SP SP - 1 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW (SP), SP SP + 1 rpH (SP + 1), rpL (SP), SP SP + 2 SP word SP AX AX SP PC addr16 PC PC + 2 + jdisp8 PCH A, PCL X PC PC + 2 + jdisp8 if CY = 1 PC PC + 2 + jdisp8 if CY = 0 PC PC + 2 + jdisp8 if Z = 1 PC PC + 2 + jdisp8 if Z = 0 R R R R R R !addr16 3 7 - CALLF !addr11 2 5 - CALLT Call/return BRK www..com RET [addr5] 1 6 - 1 6 - 1 6 - RETI 1 6 - RETB PSW PUSH rp Stack manipulate PSW POP rp SP, #word MOVW SP, AX AX, SP Unconditional branch !addr16 BR $addr16 AX BC Conditional BNC branch BZ BNZ $addr16 $addr16 $addr16 $addr16 1 1 1 1 1 4 2 2 3 2 2 2 2 2 2 6 2 4 2 4 - - - 6 6 8 6 6 6 6 - - - - - 10 8 8 - - - - - - - R RR Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 272 CHAPTER 23 INSTRUCTION SET Instruction Mnemonic Group Clock Operands saddr.bit, $addr16 sfr.bit, $addr16 Byte Note 1 Note 2 Flag Operation Z AC CY PC PC + 3 + jdisp8 if (saddr.bit) = 1 PC PC + 4 + jdisp8 if sfr.bit = 1 PC PC + 3 + jdisp8 if A.bit = 1 PC PC + 3 + jdisp8 if PSW.bit = 1 PC PC + 3 + jdisp8 if (HL).bit = 1 PC PC + 4 + jdisp8 if (saddr.bit) = 0 PC PC + 4 + jdisp8 if sfr.bit = 0 PC PC + 3 + jdisp8 if A.bit = 0 PC PC + 4 + jdisp8 if PSW.bit = 0 PC PC + 3 + jdisp8 if (HL).bit = 0 PC PC + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) PC PC + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit PC PC + 3 + jdisp8 if A.bit = 1 then reset A.bit PC PC + 4 + jdisp8 if PSW.bit = 1 then reset PSW.bit PC PC + 3 + jdisp8 if (HL).bit = 1 then reset (HL).bit B B - 1, then PC PC + 2 + jdisp8 if B 0 C C - 1, then PC PC + 2 + jdisp8 if C 0 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if (saddr) 0 RBS1, 0 n No Operation IE 1 (Enable Interrupt) IE 0 (Disable Interrupt) Set HALT Mode Set STOP Mode x x x 3 4 3 3 3 4 4 3 4 3 4 8 - 8 - 10 10 - 8 - 10 10 9 11 - 9 11 11 11 - 11 11 12 BT A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 saddr.bit, $addr16 sfr.bit, $addr16 BF A.bit, $addr16 PSW.bit, $addr16 www..com Conditional branch BTCLR [HL].bit, $addr16 saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16 B, $addr16 DBNZ C, $addr16 saddr, $addr16 SEL NOP RBn 4 3 4 3 2 2 3 2 1 2 2 2 2 - 8 - 10 6 6 8 4 2 - - 6 6 12 - 12 12 - - 10 - - 6 6 - - CPU control EI DI HALT STOP Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access 2. When an area except the internal high-speed RAM area is accessed Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC). 273 CHAPTER 23 INSTRUCTION SET 23.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ www..com 274 CHAPTER 23 INSTRUCTION SET Second Operand #byte First Operand A ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP r MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP B, C sfr saddr MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP !addr16 PSW MOV MOV MOV MOV MOV MOV XCH MOV XCH ADD MOV XCH ADD MOV MOV XCH MOV XCH ADD A r Note sfr saddr !addr16 PSW [DE] [HL] [HL + byte] [HL + B] $addr16 [HL + C] 1 ROR ROL RORC ROLC None MOV XCH ADD ADDC ADDC SUB SUB SUBC SUBC AND AND OR XOR CMP OR XOR CMP ADDC ADDC SUB SUB SUBC SUBC AND AND OR XOR CMP OR XOR CMP www..com INC DEC DBNZ DBNZ INC DEC PUSH POP [DE] [HL] MOV MOV ROR4 ROL4 [HL + byte] [HL + B] [HL + C] X C Note Except r = A MOV MULU DIVUW 275 CHAPTER 23 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand #word 1st Operand AX ADDW SUBW CMPW rp MOVW MOVW Note INCW DECW PUSH www..com AX rp Note MOVW XCHW sfrp MOVW saddrp MOVW !addr16 MOVW SP MOVW None POP MOVW MOVW MOVW MOVW MOVW MOVW MOVW sfrp saddrp !addr16 SP Note Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second Operand A.bit First Operand A.bit MOV1 BT BF BTCLR sfr.bit MOV1 BT BF BTCLR saddr.bit MOV1 BT BF BTCLR PSW.bit MOV1 BT BF BTCLR [HL].bit MOV1 BT BF BTCLR CY MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None 276 CHAPTER 23 INSTRUCTION SET (4) Call/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand AX First Operand Basic instruction BR CALL BR CALLF CALLT BR BC BNC BZ BNZ Compound www..com !addr16 !addr11 [addr5] $addr16 BT BF BTCLR DBNZ instruction (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP 277 [MEMO] www..com 278 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the PD780973 Subseries. Figure A-1 shows the development tool configuration. www..com 279 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (1/2) (1) When using in-circuit emulator IE-78K0-NS Language Processing Software * Assembler package * C compiler package * C library source file * Device file Debugging Tools www..com * System simulator * Integrated debugger * Device file Embedded Software * Real-time OS * OS Host Machine (PC) Interface adapter, PC card interface, etc. Flash memory writing environment Flash programmer In-circuit emulator Emulation board Power unit On-chip flash memory version Emulation probe Conversion socket or conversion adapter Target system 280 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration (2/2) (2) When using in-circuit emulator IE-78001-R-A Language Processing Software * Assembler package * C compiler package * C library source file * Device file Debugging Tools * System simulator * Integrated debugger * Device file www..com Embedded Software * Real-time OS * OS Host Machine (PC or EWS) Interface board Flash memory writing environment Flash programmer In-circuit emulator Interface adapter CPU core board I/O board Probe board On-chip flash memory version Emulation probe Conversion socket or conversion adapter Target system Remark The tool enclosed in a broken line depends on the development environment. Refer to A.3.1 Hardware. 281 APPENDIX A DEVELOPMENT TOOLS A.1 Language Processing Software RA78K/0 Assembler Package This assembler converts programs written in mnemonics into an object code executable with a microcontroller. Further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler is used in combination with an optional device file (DF780974). Notes 1, 2 This file contains information peculiar to the device. This file is used in combination with each optional tools RA78K/0, CC78K/0, SM78K0, ID78K0-NS, and ID78K0. Supported OS and host machine depend on each tool. Part Number: SxxxxDF780974 CC78K/0-L C Library Source File This is a source of functions configuring the object library included in the C compiler package. It is required for matching the object library included in the C compiler package with to the customer's specifications. Operation environment does not depend on OS because the source file is used. Part Number: SxxxxCC78K0-L Notes 1. The DF780974 is used in common with the RA78K/0, CC78K/0, SM78K0, ID78K0-NS, and ID78K0. 2. Under development Remark xxxx in the part number differs depending on the host machine and OS used. 282 APPENDIX A DEVELOPMENT TOOLS SxxxxRA78K0 SxxxxCC78K0 SxxxxDF780974 SxxxxCC78K0-L xxxx AA13 AB13 BB13 www..com 3P16 3K13 3K15 3R13 HP9000 Series 700TM SPARCstationTM NEWSTM (RISC) Host Machine PC-9800 Series IBM PC/ATTM and compatibles OS Windows Japanese version Windows Japanese version Windows English version Notes 1, 2 Supply Medium 3.5-inch 2HD FD 3.5-inch 2HC FD Notes 1, 2 Notes 1, 2 HP-UXTM (Rel. 9.05) SunOSTM (Rel. 4.1.4) NEWS-OSTM (Rel. 6.1) DAT (DDS) 3.5-inch 2HC FD 1/4-inch CGMT 3.5-inch 2HC FD Notes 1. DOS is also supported. 2. WindowsNTTM is not supported. A.2 Flash Memory Writing Tools Flashpro II (FL-PR2) Flash Writer Dedicated flash writer for microcontrollers with on-chip flash memory. Remark Flashpro II is a product of Naitou Densei Machidaseisakusho Co., Ltd. Naitou Densei Machidaseisakusho Co., Ltd. (TEL +81-44-822-3813) 283 APPENDIX A DEVELOPMENT TOOLS A.3 Debugging Tools A.3.1 Hardware (1/2) (1) When using in-circuit emulator IE-78K0-NS IE-78K0-NS Note In-circuit Emulator This in-circuit emulator is used to debug hardware and software when developing application systems using the 78K/0 Series. It supports the integrated debugger (ID78K0-NS). This emulator is used in combination with a power unit, an emulation probe, and an interface adapter for connection to a host machine. This is an adapter for power supply from a receptacle of 100-V to 240-V AC. IE-70000-MC-PS-B Power Unit IE-70000-98-IF-C Note www..com Interface Adapter IE-70000-CD-IF Note PC Card Interface IE-70000-PC-IF-C Note Interface Adapter IE-780974-NS-EM1 Note Emulation Board EP-80GF-NS Emulation Probe TGF-080RAP This adapter is required when using the PC-9800 Series computer (except notebook type) as the IE-78K0-NS host machine. These PC card and interface cable are required when using a PC-9800 Series notebook as the IE-78K0-NS host machine. This adapter is required when using an IBM PC/AT or compatible as the IE-78K0-NS host machine. This board is used to emulate the peripheral hardware that is peculiar to the device. This board is used in combination with an in-circuit emulator. This probe is used to connect an in-circuit emulator and target system. It is for 80-pin plastic QFPs (GF-3B9 type). This conversion adapter is used to connect a target system board designed to allow mounting of an 80-pin plastic QFP (GF-3B9 type) and the EP80GF-NS. Conversion Adapter (Refer to Figure A-2) Note Under development Remarks 1. TGF-080RAP is a product of TOKYO ELETECH Corporation. For inquiry: DAIMARU KOUGYOU Corporation Phone: +81-3-3820-7112 Tokyo Electronic Components Division +81-6-244-6672 Osaka Electronic Components Division 2. The TGF-080RAP is sold in single units. 284 APPENDIX A DEVELOPMENT TOOLS A.3.1 Hardware (2/2) (2) When using in-circuit emulator IE-78001-R-A IE-78001-R-A Note In-circuit Emulator This in-circuit emulator is used to debug hardware and software when developing application systems using the 78K/0 Series. It supports the integrated debugger (ID78K0). This emulator is used in combination with an emulation probe and an interface adapter for connection to a host machine. This adapter is required when using the PC-9800 Series computer (except notebook type) as the IE-78001-R-A host machine. This adapter is required when using an IBM PC/AT or compatible as the IE-78001-R-A host machine. This is an adapter and cable when an EWS is used as the host machine for the IE78001-R-A and is connected to the board in the IE-78001-R-A. 10Base-5 is supported as EthernetTM. For the other methods, a commercially available conversion adapter is necessary. This board is used to emulate a 78K/0 Series CPU. This board is used in combination with an in-circuit emulator and probe board. This board is used to perform mask option settings and pin connection changes. This probe is used to connect an in-circuit emulator and target system. It is for 80-pin plastic QFPs (GF-3B9 type). An 80-pin conversion socket (TGF-080RAP) is included to facilitate target system development. TGF-080RAP Conversion Adapter (See Figure A-2) This conversion adapter is used to connect a target system board designed to allow mounting of an 80-pin plastic QFP (GF-3B9 type) and the EP-80GF-SL. IE-70000-98-IF-B or IE-70000-98-IF-C Note Interface Adapter IE-70000-PC-IF-B or IE-70000-PC-IF-C Note Interface Adapter www..com IE-78000-R-SV3 Interface Adapter IE-78K0-SL-EM Note CPU Core Board IE-780974-SL-EM1 Probe Board EP-80GF-SL Emulation Probe Note Under development Remarks 1. TGF-080RAP is a product of TOKYO ELETECH Corporation. For inquiry: DAIMARU KOUGYOU Corporation Phone: +81-3-3820-7112 Tokyo Electronic Components Division +81-6-244-6672 Osaka Electronic Components Division 2. The TGF-080RAP is sold in single units. 285 APPENDIX A DEVELOPMENT TOOLS A.3.2 Software (1/2) SM78K0 System Simulator This system simulator is used to perform debugging at C source level or assembler level while simulating the operation of the target system on a host machine. The SM78K0 operates on Windows. Use of the SM78K0 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an in-circuit emulator, thereby providing higher development efficiency and software quality. The SM78K0 is used in combination with the optional device file (DF780974). Part Number: SxxxxSM78K0 Remark xxxx in the part number differs depending on the host machine and OS used. www..com SxxxxSM78K0 xxxx AA13 AB13 BB13 Host Machine PC-9800 Series IBM PC/AT and compatibles OS Windows Japanese version Windows Japanese version Windows English version Note Note Supply Medium 3.5-inch 2HD FD 3.5-inch 2HC FD Note Note WindowsNT is not supported. 286 APPENDIX A DEVELOPMENT TOOLS A.3.2 Software (2/2) ID78K0-NS Note Integrated Debugger (Supports in-circuit emulator IE-78K0-NS) ID78K0 Integrated Debugger (Supports in-circuit emulator IE-78001-R-A) This is a control program used to debug the 78K/0 Series. The graphical user interfaces employed are Windows for personal computers and OSF/ MotifTM for EWSs, offering the standard appearance and operability typical of these interfaces. Further, debugging functions supporting C language are reinforced, and the trace result can be displayed in C language level by using a window integrating function that associates the source program, disassemble display, and memory display with the trace result. In addition, it can enhance the debugging efficiency of a program using a real-time OS by incorporating function expansion modules such as a task debugger and system performance analyzer. This debugger is used in combination with an optional device file (DF780974). Part Number: SxxxxID78K0-NS, SxxxxID78K0 www..com Note Under development Remark xxxx in the part number differs depending on the host machine and OS used. SxxxxID78K0-NS xxxx AA13 AB13 BB13 Host Machine PC-9800 Series IBM PC/AT and compatibles OS Windows Japanese version Note Windows Japanese version Windows English version Note Note Supply Medium 3.5-inch 2HD FD 3.5-inch 2HC FD Note WindowsNT is not supported. SxxxxID78K0 xxxx AA13 AB13 BB13 3P16 3K13 3K15 3R13 NEWS (RISC) NEWS-OS (Rel. 6.1) HP9000 Series 700 SPARCstation Host Machine PC-9800 Series IBM PC/AT and compatibles OS Windows Japanese version Windows Japanese version Windows English version HP-UX (Rel. 9.05) SunOS (Rel. 4.1.4) Note Note Supply Medium 3.5-inch 2HD FD 3.5-inch 2HC FD Note DAT (DDS) 3.5-inch 2HC FD 1/4-inch CGMT 3.5-inch 2HC FD Note WindowsNT is not supported. 287 APPENDIX A DEVELOPMENT TOOLS A.4 Upgrading Former In-circuit Emulator for 78K/0 Series to IE-78001-R-A If you have a former in-circuit emulator for the 78K/0 Series (IE-78000-R or IE-78000-R-A), your in-circuit emulator can be upgraded to be equivalent to the IE-78001-R-A in-circuit emulator by simply replacing the break board with the IE-78001-R-BK (under development). Table A-1. Upgrading Former In-circuit Emulator for 78K/0 Series to IE-78001-R-A In-circuit Emulator IE-78000-R IE-78000-R-A www..com Required Not required Cabinet Upgrading Note Board to be Purchased IE-78001-R-BK Note To upgrade your cabinet, bring it to NEC. 288 APPENDIX A DEVELOPMENT TOOLS Dimensions of Conversion Adapter (TGF-080RAP) Figure A-2. Dimensions of TGF-080RAP (Reference) Q D A B C T V P R S T d e MNO XWU g Protrusion height w w w . D a t a S h e e G4 U . c o m Ht F E bc f i h V I J K L Y Z a k l j m o r n q p s u t u w v ITEM A B C D E F G H I J K L M N O P Q R S T U V W X Y Z MILLIMETERS 20.65 14.1 0.8x15=12 0.8 16.4 18.8 21.2 23.6 10.0 12.4 14.8 17.2 0.8x23=18.4 20.5 27.05 0.8 C 2.0 18.65 13.35 1.325 19.75 1.125 23.55 27.05 10.6 17.1 INCHES 0.813 0.555 0.031x0.591=0.472 0.031 0.646 0.740 0.835 0.929 0.394 0.488 0.583 0.677 0.031x0.906=0.724 0.807 1.065 0.031 C 0.079 0.734 0.526 0.052 0.778 0.044 0.927 1.065 0.417 0.673 ITEM a b c d e f g h i j k l m n o p q r s t u v w MILLIMETERS 20.65 14.40 18.8 7.7 5.3 5.0 4- 1.3 1.8 9.5 3.55 0.9 INCHES 0.813 0.567 0.740 0.303 0.209 0.197 4- 0.051 0.071 0.374 0.3 (16.95) 7.35 1.2 1.85 3.5 2.0 0.25 13.6 1.2 2.4 2.7 0.140 0.035 0.012 (0.667) 0.289 0.047 0.073 0.138 0.079 0.010 0.535 0.047 0.094 0.106 TGF-080RAP-G0 Note: Product of TOKYO ELETECH CORPORATION. 289 [MEMO] www..com 290 APPENDIX B EMBEDDED SOFTWARE For efficient development and maintenance of the PD780973 Subseries, the following embedded software products are available. Real-Time OS (1/2) RX78K/0 Real-time OS RX78K/0 is a real-time OS conforming with the ITRON specifications. Tool (configurator) for generating nucleus of RX78K/0 and plural information tables is supplied. Used in combination with an optional assembler package (RA78K/0) and device file (DF780974). www..com Caution When purchasing the RX78K/0, fill in the purchase application form in advance and sign the User Agreement. Remark xxxx and in the part number differ depending on the host machine and OS used. SxxxxRX78013- 001 100K 001M 010M S01 Source program Product Outline Evaluation object Object for mass-produced product Upper Limit of Mass-Production Quantity Do not use for mass-produced products. 0.1 million units 1 million units 10 million units Source program for mass-produced object xxxx AA13 AB13 BB13 3P16 3K13 3K15 3R13 Host Machine PC-9800 Series IBM PC/AT and compatibles OS Windows Japanese version Windows Japanese version Notes 1, 2 Notes 1, 2 Supply Medium 3.5-inch 2HD FD 3.5-inch 2HC FD Windows English version Notes 1, 2 HP9000 Series 700 SPARCstation HP-UX (Rel. 9.05) SunOS (Rel. 4.1.4) DAT (DDS) 3.5-inch 2HC FD 1/4-inch CGMT NEWS (RISC) NEWS-OS (Rel. 6.1) 3.5-inch 2HC FD Notes 1. DOS is also supported. 2. WindowsNT is not supported. 291 APPENDIX B EMBEDDED SOFTWARE Real-Time OS (2/2) MX78K0 OS lTRON specification subset OS. Nucleus of MX78K0 is supplied. This OS performs task management, event management, and time management. It controls the task execution sequence for task management and selects the task to be executed next. Part number: SxxxxMX78K0- Remark xxxx and in the part number differ depending on the host machine and OS used. www..com SxxxxMX78K0- 001 xx S01 Product Outline Evaluation object Object for mass-produced product Source program Use for trial product. Use for mass-produced product. Can be purchased only when object for mass-produced product is purchased. Note xxxx AA13 AB13 BB13 3P16 3K13 3K15 3R13 Host Machine PC-9800 Series IBM PC/AT and compatibles OS Windows Japanese version Notes 1, 2 Supply Medium 3.5-inch 2HD FD 3.5-inch 2HC FD Windows Japanese version Notes 1, 2 Windows English version Notes 1, 2 HP9000 Series 700 SPARCstation HP-UX (Rel. 9.05) SunOS (Rel. 4.1.4) DAT (DDS) 3.5-inch 2HC FD 1/4-inch CGMT NEWS (RISC) NEWS-OS (Rel. 6.1) 3.5-inch 2HC FD Notes 1. DOS is also supported. 2. WindowsNT is not supported. 292 APPENDIX C REGISTER INDEX C.1 Register Index (In Alphabetical Order with Respect to Register Name) [A] A/D conversion result register (ADCR1) ... 150 A/D converter mode register (ADM1) ... 152 Analog input channel specification register (ADS1) ... 153 Asynchronous serial interface mode register (ASIM) ... 167, 171, 172 Asynchronous serial interface status register (ASIS) ... 169, 173 www..com [B] Baud rate generator control register (BRGC) ... 169, 174 [C] Capture pulse control register (CRC0) ... 104 Capture register 00 (CR00) ... 102 Capture register 01 (CR01) ... 102 Capture register 02 (CR02) ... 102 Clock output selection register (CKS) ... 146 Compare control register 1 (MCMPC1) ... 217 Compare control register 2 (MCMPC2) ... 217 Compare control register 3 (MCMPC3) ... 217 Compare control register 4 (MCMPC4) ... 217 Compare register 10 (MCMP10) ... 215 Compare register 11 (MCMP11) ... 215 Compare register 20 (MCMP20) ... 215 Compare register 21 (MCMP21) ... 215 Compare register 30 (MCMP30) ... 215 Compare register 31 (MCMP31) ... 215 Compare register 40 (MCMP40) ... 215 Compare register 41 (MCMP41) ... 215 [D] D/A converter mode register (DAM1) ... 163 [E] EEPROM write control register (EEWC) ... 69 8-bit compare register 1 (CR1) ... 112 8-bit compare register 2 (CR2) ... 121 8-bit compare register 3 (CR3) ... 121 8-bit counter 1 (TM1) ... 112 8-bit counter 2 (TM2) ... 121 8-bit counter 3 (TM3) ... 121 8-bit timer mode control register 1 (TMC1) ... 114 8-bit timer mode control register 2 (TMC2) ... 123 8-bit timer mode control register 3 (TMC3) ... 123 293 APPENDIX C REGISTER INDEX External interrupt falling edge enable register (EGN) ... 231 External interrupt rising edge enable register (EGP) ... 231 [I] Interrupt mask flag register 0H (MK0H) ... 229 Interrupt mask flag register 0L (MK0L) ... 229 Interrupt mask flag register 1L (MK1L) ... 229 Interrupt request flag register 0H (IF0H) ... 228 Interrupt request flag register 0L (IF0L) ... 228 Interrupt request flag register 1L (IF1L) ... 228 [L] www..com LCD display control register (LCDC) ... 193 LCD display mode register (LCDM) ... 192 LCD timer control register (LCDTM) ... 203 [M] Memory size switching register (IMS) ... 258 [O] Oscillation stabilization time select register (OSTS) ... 246 Oscillator mode register (OSCM) ... 91 [P] Port 0 (P0) ... 75 Port 1 (P1) ... 76 Port 2 (P2) ... 77 Port 3 (P3) ... 78 Port 4 (P4) ... 79 Port 5 (P5) ... 80 Port 6 (P6) ... 81 Port 8 (P8) ... 82 Port 9 (P9) ... 83 Port mode control register (PMC) ... 217 Port mode register 0 (PM0) ... 84 Port mode register 2 (PM2) ... 84 Port mode register 3 (PM3) ... 84 Port mode register 4 (PM4) ... 84 Port mode register 5 (PM5) ... 84 Port mode register 6 (PM6) ... 84, 147 Port mode register 8 (PM8) ... 84 Port mode register 9 (PM9) ... 84 Power-fail compare mode register (PFM) ... 154 Power-fail compare threshold value register (PFT) ... 154 Prescaler mode register (PRM0) ... 105, 232 Priority specify flag register 0H (PR0H) ... 230 Priority specify flag register 0L (PR0L) ... 230 Priority specify flag register 1L (PR1L) ... 230 Processor clock control register (PCC) ... 90 Pull-up resistor option register (PU0) ... 87 294 APPENDIX C REGISTER INDEX [R] Receive buffer register (RXB) ... 166 [S] Serial I/O shift register (SIO) ... 184 Serial operation mode register (CSIM) ... 185, 186 16-bit timer mode control register (TMC0) ... 103 16-bit timer register (TM0) ... 102 Sound generator amplitude register (SGAM) ... 210 Sound generator buzzer control register (SGBR) ... 209 Sound generator control register (SGCR) ... 207 www..com [T] Timer clock select register 1 (TCL1) ... 113 Timer clock select register 2 (TCL2) ... 122 Timer clock select register 3 (TCL3) ... 122 Timer mode control register (MCNTC) ... 216 Transmit shift register (TXS) ... 166 [W] Watch timer mode control register (WTM) ... 135 Watchdog timer clock select register (WDCS) ... 141 Watchdog timer mode register (WDTM) ... 142 295 APPENDIX C REGISTER INDEX C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) [A] ADCR1 ADM1 ADS1 ASIM ASIS : : : : : A/D conversion result register ... 150 A/D converter mode register ... 152 Analog input channel specification register ... 153 Asynchronous serial interface mode register ... 167, 171, 172 Asynchronous serial interface status register ... 169, 173 [B] BRGC www..com [C] : Baud rate generator control register ... 169, 174 CKS CR00 CR01 CR02 CR1 CR2 CR3 CRC0 CSIM : : : : : : : : : Clock output selection register ... 146 Capture register 00 ... 102 Capture register 01 ... 102 Capture register 02 ... 102 8-bit compare register 1 ... 112 8-bit compare register 2 ... 121 8-bit compare register 3 ... 121 Capture pulse control register ... 104 Serial operation mode register ... 185, 186 [D] DAM1 : D/A converter mode register ... 163 [E] EEWC EGN EGP : : : EEPROM write control register ... 69 External interrupt falling edge enable register ... 231 External interrupt rising edge enable register ... 231 [I] IF0H IF0L IF1L IMS : : : : Interrupt request flag register 0H ... 228 Interrupt request flag register 0L ... 228 Interrupt request flag register 1L ... 228 Memory size switching register ... 258 [L] LCDC LCDM LCDTM : : : LCD display control register ... 193 LCD display mode register ... 192 LCD timer control register ... 203 [M] MCMP10 : MCMP11 : MCMP20 : MCMP21 : MCMP30 : MCMP31 : Compare register 10 ... 215 Compare register 11 ... 215 Compare register 20 ... 215 Compare register 21 ... 215 Compare register 30 ... 215 Compare register 31 ... 215 296 APPENDIX C REGISTER INDEX MCMP40 : MCMP41 : MCMPC1 : MCMPC2 : MCMPC3 : MCMPC4 : MCNTC MK0H MK0L MK1L : : : : Compare register 40 ... 215 Compare register 41 ... 215 Compare control register 1 ... 217 Compare control register 2 ... 217 Compare control register 3 ... 217 Compare control register 4 ... 217 Timer mode control register ... 216 Interrupt mask flag register 0H ... 229 Interrupt mask flag register 0L ... 229 Interrupt mask flag register 1L ... 229 [O] www..com OSCM : : Oscillator mode register ... 91 Oscillation stabilization time select register ... 246 OSTS [P] P0 P1 P2 P3 P4 P5 P6 P8 P9 PCC PFM PFT PM0 PM2 PM3 PM4 PM5 PM6 PM8 PM9 PMC PR0H PR0L PR1L PRM0 PU0 : : : : : : : : : : : : : : : : : : : : : : : : : : Port 0 ... 75 Port 1 ... 76 Port 2 ... 77 Port 3 ... 78 Port 4 ... 79 Port 5 ... 80 Port 6 ... 81 Port 8 ... 82 Port 9 ... 83 Processor clock control register ... 90 Power-fail compare mode register ... 154 Power-fail compare threshold value register ... 154 Port mode register 0 ... 84 Port mode register 2 ... 84 Port mode register 3 ... 84 Port mode register 4 ... 84 Port mode register 5 ... 84 Port mode register 6 ... 84, 147 Port mode register 8 ... 84 Port mode register 9 ... 84 Port mode control register ... 217 Priority specify flag register 0H ... 230 Priority specify flag register 0L ... 230 Priority specify flag register 1L ... 230 Prescaler mode register ... 105, 232 Pull-up resistor option register ... 87 [R] RXB : Receive buffer register ... 166 [S] SGAM SGBR : : Sound generator amplitude register ... 210 Sound generator buzzer control register ... 209 297 APPENDIX C REGISTER INDEX SGCR SIO : : Sound generator control register ... 207 Serial I/O shift register ... 184 [T] TCL1 TCL2 TCL3 TM0 TM1 TM2 TM3 TMC0 www..com TMC1 : : : : : : : : : : : : Timer clock select register 1 ... 113 Timer clock select register 2 ... 122 Timer clock select register 3 ... 122 16-bit timer register ... 102 8-bit counter 1 ... 112 8-bit counter 2 ... 121 8-bit counter 3 ... 121 16-bit timer mode control register ... 103 8-bit timer mode control register 1 ... 114 8-bit timer mode control register 2 ... 123 8-bit timer mode control register 3 ... 123 Transmit shift register ... 166 TMC2 TMC3 TXS [W] WDCS WDTM WTM : : : Watchdog timer clock select register ... 141 Watchdog timer mode register ... 142 Watch timer mode control register ... 135 298 APPENDIX D REVISION HISTORY The revision history of this edition is listed below. "Chapter" indicates the chapter of the previous edition where the revision was made. (1/2) Edition Second Revisions Table 2-1. Pin Input/Output Circuit Types Correction of ports 8 and 9 input/output circuit types Figure 2-1. I/O Circuits of Pins Change of type 17-A to type 17-G Addition of oscillator mode register to Table 3-5. Special Function Register List 4.1 EEPROM Functions Change of the number of rewrite frequency per 1 byte as follows: 10,000 times 100,000 times 5.2.3 Port 2 * Correction of description * Correction of Figure 5-4. P20 to P27 Block Diagram 5.2.4 Port 3 * Correction of description * Correction of Figure 5-5. P30 to P37 Block Diagram 5.2.8 Port 8 * Correction of description * Addition of Figure 5-9. P81 Block Diagram * Correction of Figure 5-10. P82 to P87 Block Diagram 5.2.9 Port 9 * Correction of description * Correction of Figure 5-11. P90 to P97 Block Diagram Table 5-3. Port Mode Register and Output Latch Settings when Using Alternate Functions * Change of Pxx setting values of P20 to P27 and P30 to P37 from 0 to x * Change of Note 2 Addition of Note in Figure 5-13. Port Mode Register (PM2, PM3) Format * Addition of oscillator mode register to Table 6-1. Clock Generator Configuration * Change of Figure 6-1. Clock Generator Block Diagram * Addition of (2) Oscillator mode register (OSCM) to 6.3 Clock Generator Control Register * Addition of explanation of oscillator mode register to 6.5 Operation of Clock Generator 13.6 Cautions on Emulation Change of in-circuit emulator of (1) D/A converter mode register (DAM1) as follows: IE-78001-R-A IE78K0-NS Addition of (2) A/D converter of IE-780974-NS-EM1 CHAPTER 6 CLOCK GENERATOR CHAPTER 3 CPU ARCHITECTURE Chapter CHAPTER 2 PIN FUNCTION www..com CHAPTER 4 EEPROM CHAPTER 5 PORT FUNCTIONS CHAPTER 13 A/D CONVERTER 16.9 Cautions on Emulation CHAPTER 16 Change of in-circuit emulator of (1) LCD timer control register (LCDTM) LCD CONTROLLER/DRIVER as follows: IE-78001-R-A IE78K0-NS 299 APPENDIX D REVISION HISTORY (2/2) Edition Second Revisions 17.1 Sound Generator Function Correction of description on (1) Basic cycle output signal (with/without amplitude) 18.2 Meter Controller/Driver Configuration Addition of Cautions to (1) Free running up counter (MCNT) Table 20-1. HALT Mode Operating Status Correction of HALT mode operating status of A/D converter Operable Operation stops Addition of oscillator mode register to Table 21-1. Hardware Status after Reset www..com Change of Note in Table 22-1. Differences between PD78F0974 and PD780973(A) * Support of in-circuit emulator IE-78K0-NS * Change in supported OS * Addition of A.4 Upgrading Former In-circuit Emulator for 78K/0 Series to IE-78001-R-A * Deletion of OS for IBM PC from previous edition * Deletion of Development Environment when Using IE-78000-R-A from previous edition * Change in supported OS * Deletion of Fuzzy Inference Development Support System from previous edition Chapter CHAPTER 17 SOUND GENERATOR CHAPTER 18 METER CONTROLLER/DRIVER CHAPTER 20 STANDBY FUNCTION CHAPTER 21 RESET FUNCTION CHAPTER 22 PD78F0974 APPENDIX A DEVELOPMENT TOOLS APPENDIX B EMBEDDED SOFTWARE 300 Facsimile Message From: Name Company www..com Tel. FAX Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation. Please complete this form whenever you'd like to report errors or suggest improvements to us. Address Thank you for your kind support. North America Hong Kong, Philippines, Oceania NEC Electronics Inc. NEC Electronics Hong Kong Ltd. Corporate Communications Dept. Fax: +852-2886-9022/9044 Fax: 1-800-729-9288 1-408-588-6130 Korea Europe NEC Electronics Hong Kong Ltd. NEC Electronics (Europe) GmbH Seoul Branch Technical Documentation Dept. Fax: 02-528-4411 Fax: +49-211-6503-274 South America NEC do Brasil S.A. Fax: +55-11-6465-6829 Taiwan NEC Electronics Taiwan Ltd. Fax: 02-719-5951 Asian Nations except Philippines NEC Electronics Singapore Pte. Ltd. Fax: +65-250-3583 Japan NEC Semiconductor Technical Hotline Fax: 044-548-7900 I would like to report the following error/make the following suggestion: Document title: Document number: Page number: If possible, please fax the referenced page or drawing. Document Rating Clarity Technical Accuracy Organization CS 98.2 Excellent Good Acceptable Poor |
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